A 100 nm CMOS technology with "sidewall-notched" 40 nm transistors and SiC-capped Cu/VLK interconnects for high performance microprocessor applications

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 2002, Pages 66-67

  Nakai, S ^a   Takao, Y ^a   Otsuka, S ^a   Sugiyama, K ^a   Ohta, H ^a   Yamanoue, A ^a   Iriyama, Y ^a   Nanjyo, R ^a   Sekino, S ^a   Nagai, H ^a   Naitoh, K ^a   Nakamura, R ^a   Sambonsugi, Y ^a   Tagawa, Y ^a   Horiguchi, N ^a   Yamamoto, T ^a   Kojima, M ^a   Satoh, S ^a   Sugatani, S ^a   Sugii, T ^a   Kase, M ^a   Suzuki, K ^a   Nakaishi, M ^a   Miyajima, M ^a   Ohba, T ^a   Hanyu, I ^a   Yanai, K ^a   more..

^a FUJITSU LABORATORIES LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

DIELECTRIC MATERIALS; MASKS; MICROPROCESSOR CHIPS; PHASE SHIFT; PHOTOLITHOGRAPHY; SILICON CARBIDE; STATIC RANDOM ACCESS STORAGE; TRANSISTORS;

OPTICAL PROXIMITY CORRECTION (OPC);

CMOS INTEGRATED CIRCUITS;

EID: 0036052955     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)