The impact of device scaling and power supply change on CMOS gate performance

IEEE Electron Device Letters

Volumn 17, Issue 5, 1996, Pages 202-204

  Chen, Kai ^b   Wann, H Clement ^b   Ko, Ping K ^a,b   Hu, Chenming ^a,b  

^a IEEE

^b UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; ELECTRIC CURRENTS; ELECTRIC INVERTERS; ELECTRIC POWER SUPPLIES TO APPARATUS; ELECTRON TRANSPORT PROPERTIES; ELECTRONS; GATES (TRANSISTOR); MATHEMATICAL MODELS; PERFORMANCE; RELIABILITY;

DEVICE SCALING; SATURATION DRAIN CURRENT;

CMOS INTEGRATED CIRCUITS;

EID: 0030151891     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/55.491829     Document Type: Article

References (5)

1. ox and its application in device modelling and optimization," in Proc. 1995 Int. Semiconduct. Dev. Res. Conf., Virginia, Dec. 6-8, 1995, pp. 607-610.
2. K. Chen, H. C. Wann, J. Duster, D. Pramanik, S. Nariani, P. K. Ko, and C. Hu, "An accurate semi-empirical saturation drain current model for N-MOSFET," IEEE Electron Device Lett., vol. 17, no. 3, pp. 145-147, Mar. 1996.
3. K. Y. Toh, P. K. Ko, and R. G. Meyer, "An engineering model for short-channel mos devices," IEEE J. Solid State Circuits, vol. 23, pp. 950-958, Aug. 1988.
4. C. Hu, "Future CMOS scaling and reliability," Proc. IEEE, (invited paper), vol. 81, no. 5, May 1993.
5. D. Liu and C. Svensson, "Trading speed for low power by choice of supply and threshold voltages," IEEE J. Solid State Circuits, vol. 28, no. 1, Jan. 1993.