60 nm gate length dual-Vt CMOS for high performance applications

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 2002, Pages 124-125

  Mehrotra, M ^a   Wu, J ^a   Jain, A ^a   Laaksonen, T ^a   Kim, K ^a   Bather, W ^a   Koshy, R ^a   Chen, J ^a   Jacobs, J ^a   Ukraintsev, V ^a   Olsen, L ^a   DeLoach, J ^a   Mehigan, J ^a   Agarwal, R ^a   Walsh, S ^a   Sekel, D ^a   Tsung, L ^a   Vaidyanathan, M ^a   Trentman, B ^a   Liu, K ^a   Aur, S ^a   Khamankar, R ^a   Nicollian, P ^a   Jiang, Q ^a   Xu, Y ^a   Campbell, B ^a   Tiner, P ^a   Wise, R ^a   Scott, D ^a   Rodder, M ^a   more..

^a TEXAS INSTRUMENTS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DIELECTRIC MATERIALS; DOPING (ADDITIVES); MOSFET DEVICES; NITRIDING; PLASMA THEORY;

DOPANT ACTIVATION; DOPANT LOSS;

CMOS INTEGRATED CIRCUITS;

EID: 0036051615     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)