0.65 V device design with high-performance and high-density 100 nm CMOS technology for low operation power application

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 2002, Pages 122-123

  Takao, Y ^a   Nakai, S ^a   Tagawa, Y ^a   Otsuka, S ^a   Sambonsugi, Y ^a   Sugiyama, K ^a   Oota, H ^a   Iriyama, Y ^a   Nanjyo, R ^a   Nagai, H ^a   Naitoh, K ^a   Nakamura, R ^a   Sekino, S ^a   Yamanoue, A ^a   Horiguchi, N ^a   Yamamoto, T ^a   Kojima, M ^a   Satoh, S ^a   Sugii, T ^a   Kase, M ^a   Suzuki, K ^a   Nakaishi, M ^a   Miyajima, M ^a   Ohba, T ^a   Hanyu, I ^a   Sugatani, S ^a   more..

^a FUJITSU LABORATORIES LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

DIELECTRIC MATERIALS; ELECTRIC POTENTIAL; ELECTRIC POWER UTILIZATION; LITHOGRAPHY; NETWORKS (CIRCUITS);

PARASITIC CAPACITANCE;

CMOS INTEGRATED CIRCUITS;

EID: 0036054243     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)