A scalable high-performance computing solution for networks on chips

IEEE Micro

Volumn 22, Issue 5, 2002, Pages 46-55

  Forsell, Martti ^a  

^a VTT TECHNICAL RESEARCH CENTRE OF FINLAND   (Finland)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER ARCHITECTURE; INTERCONNECTION NETWORKS; INTERFACES (COMPUTER); MICROPROCESSOR CHIPS; PARALLEL PROCESSING SYSTEMS;

PARALLEL PROGRAMMING;

COMPUTER NETWORKS;

EID: 0036760609     PISSN: 02721732     EISSN: None     Source Type: Journal    
DOI: 10.1109/MM.2002.1044299     Document Type: Article

References (9)

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2. L. Benini and G. De Micheli, "Networks on Chips: A New SoC Paradigm," Computer, vol. 35, no. 1, Jan. 2002, pp. 70-78.
3. S. Kumar et al., "A Network on Chip Architecture and Design Methodology," Proc. IEEE Computer Soc. Ann. Symp. VLSI (ISVLSI), IEEE CS Press, Los Alamitos, Calif., 2002, pp. 117-124.
4. M. Forsell, "MTAC: A Multithreaded VLIW Architecture for PRAM Simulation," J. Universal Computer Science, vol. 3, no. 9, 1997, pp. 1037-1055.
5. M. Forsell and V. Leppänen, "Memory Module Structures for Shared Memory Simulation," Proc. Int'l Conf. Advances in Infrastructure for Electronic Business, Science, and Education on the Internet, Scuola Superiore G. Reiss Romoli (SSGRR), L'Aquila, Italy, 2002, pp. 1-12.
6. M. Forsell, "Cacheless Instruction Fetch Mechanism for Multithreaded Processors," World Scientific and Eng. Academy and Soc. (WSEAS) Trans. Comm., vol. 1, no. 1, 2002, pp. 150-155.
7. J. Keller, C. Kessler, and J. Träff, Practical PRAM Programming, John Wiley & Sons, New York, 2000.
8. M. Dietzfelbinger et al., "Dynamic Perfect Hashing: Upper and Lower Bounds," SlAM J. Computing, vol. 23, no. 4, 1994, pp. 738-761.
9. V. Leppänen, "Studies on the Realization of PRAM," diss. 3, Turku Centre for Computer Science, Univ. of Turku, Finland, 1996.