Efficient power co-estimation techniques for system-on-chip design

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2000, Pages 27-34

  Lajolo, Marcello ^a   Raghunathan, Anand ^b   Dey, Sujit ^c   Lavagno, Luciano ^d  

^a POLITECNICO DI TORINO   (Italy)

^b NEC LABORATORIES AMERICA   (United States)

^c UNIVERSITY OF CALIFORNIA   (United States)

^d UNIVERSITY OF UDINE   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

ACCELERATION TECHNIQUE; LEVELS OF ABSTRACTION; POWER ESTIMATIONS; SPEED-UP TECHNIQUES; STATISTICAL SAMPLING; SWITCHING ACTIVITIES; SYSTEM LEVEL SIMULATION; SYSTEM ON CHIP DESIGN;

APPLICATION SPECIFIC INTEGRATED CIRCUITS; DESIGN; EXHIBITIONS; ITERATIVE METHODS; MICROPROCESSOR CHIPS; PROGRAMMABLE LOGIC CONTROLLERS; SAMPLING;

ESTIMATION;

EID: 84893689640     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2000.840011     Document Type: Conference Paper

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