Adjustable Width Linear Combinational Scan Vector Decompression

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers

Volumn , Issue , 2003, Pages 863-866

  Krishna, C V ^a   Touba, Nur A ^a  

^a The University of Texas at Austin   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BLOCK CODES; COMBINATORIAL CIRCUITS; COMPUTER ARCHITECTURE; COMPUTER HARDWARE; CONSTRAINT THEORY; DECODING; ENCODING (SYMBOLS); GATES (TRANSISTOR); VECTORS;

VECTOR COMPRESSION;

DATA COMPRESSION;

EID: 0346778706     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/iccad.2003.159776     Document Type: Conference Paper

References (21)

1. Bayraktaroglu, I., and A. Ogailoglu, "Test Volume and Application Time Reduction Through Scan Chain Concealment," Proc. of Design Autom. Conf., pp. 151-155, 2001.
2. Chandra, A., and K. Chakrabarty, "Test Data Compression for System-on-a-Chip Using Golomb Codes," Proc. of VLSI Test Symposium, pp. 113-120, 2000.
3. Chandra, A., and K. Chakrabarty, "Frequency-Directed Run Length (FOR) Codes with Application to System-on-a-Chip Test Data Compression," Proc. of VLSI Test Symp., pp. 42-47, 2001.
4. Das, D., and N.A. Touba, "Reducing Test Data Volume Using External/LBIST Hybrid Test Patterns," Proc. of International Test Conference, pp. 115-122, 2000.
5. Dorsch, R., and H.-J. Wunderlich, "Tailoring ATPG for Embedded Testing," Proc. of Int. Test Conf., pp. 530-537, 2001.
6. Hamzaoglu, I., and J.H. Patel, "Reducing Test Application Time for Full Scan Embedded Cores," Proc. of Int. Symposium on Fault Tolerant Computing, pp. 260-267, 1999.
7. Hellebrand, S., H.-G. Liang, and H.-J. Wunderlich, "A Mixed Mode BIST Scheme Based on Reseeding of Folding Counters," Proc. of Int. Test Conference, pp. 778-784, 2000.
8. Hsu, F.F., K. M. Butler, J. H. Patel, "A Case Study on the Implementation of the Illinois Scan Architecture," Proc. of International Test Conference, pp. 538-547, 2001.
9. Jas, A., and N.A. Touba, "Test Vector Decompression Via Cyclical Scan Chains and Its Application to Testing Core-Based Designs", Proc. of Int. Test Conference, pp. 458-464, 1998.
10. Jas, A., J. Ghosh-Dastidar, and N.A. Touba, "Scan Vector Compression/Decompression Using Statistical Coding", Proc. of VLSI Test Symposium, pp. 114-120, 1999.
11. Jas, A., B. Pouya, and N.A. Touba, "Virtual Scan Chains: A Means for Reducing Scan Length in Cores", Proc. of VLSI Test Symposium, pp. 73-78, 2000.
12. Könemann, B., "LFSR-Coded Test Patterns for Scan Designs, " Proc. of European Test Conference, pp. 237-242, 1991.
13. Könemann, B., "A SmartBIST Variant with Guaranteed Encoding" Proc. of Asian Test Symposium, pp. 325-330, 2001.
14. Krishna, C.V., A. Jas, and N.A. Touba, "Test Vector Encoding Using Partial LFSR Reseeding", Proc. of International Test Conference, pp. 885-893, 2001.
15. Krishna, C.V., and N.A. Touba, "Reducing Test Data Volume Using LFSR Reseeding with Seed Compression ", Proc. of International Test Conference, pp. 321-330, 2001.
16. Liang, H.-G., S. Hellebrand, and H.-J. Wunderlich, "Two-Dimensional Test Data Compression for Scan-Based Deterministic BIST," Proc. of International Test Conference, pp. 894-902, 2001.
17. Rajski, J., et al., "Embedded Deterministic Test for Low Cost Manufacturing Test," Proc. of Int. Test Conf., pp. 301-310, 2002.
18. Reda, S., and A. Orailoglu, "Reducing Test Application Time Through Test Data Mutation Encoding", Proc. of Design, Automation, and Test in Europe, pp. 387-393, 2002.
19. Reddy, S., K. Miyase, S. Kajihara, and I. Pomeranz, "On Test Data Volume Reduction for Multiple Scan Chain Designs", Proc. of VLSI Test Symposium, pp. 103-108, 2002.
20. Volkerink, E.H., A. Khoche, and S. Mitra, "Packet-based Input Test Data Compression Techniques," Proc. of International Test Conference, pp. 154-163, 2002.
21. Volkerink, E.H., and S. Mitra, "Efficient Seed Utilization for Reseeding based Compression," Proc. VLSI Test Symposium, 2003.