On test data volume reduction for multiple scan chain designs

Proceedings of the IEEE VLSI Test Symposium

Volumn 2002-January, Issue , 2002, Pages 103-108

  Reddy, S M ^a   Miyase, K ^b   Kajihara, S ^b   Pomeranz, I ^c  

^a UNIVERSITY OF IOWA   (United States)

^b KYUSHU INSTITUTE OF TECHNOLOGY   (Japan)

^c Purdue University   (United States)

Author keywords

Circuit faults; Circuit testing; Costs; Data engineering; Design engineering; Electronic equipment testing; Encoding; Microelectronics; System testing; Very large scale integration

Indexed keywords

CHAINS; COST ENGINEERING; COSTS; DATA COMPRESSION; ELECTRONIC EQUIPMENT; ELECTRONIC EQUIPMENT TESTING; ENCODING (SYMBOLS); EQUIPMENT TESTING; INTEGRATED CIRCUIT TESTING; INTEGRATION TESTING; MICROELECTRONICS; MICROPROCESSOR CHIPS; OSCILLATORS (ELECTRONIC); SEQUENTIAL CIRCUITS; TEST FACILITIES; VLSI CIRCUITS;

CIRCUIT FAULTS; CIRCUIT TESTING; DATA ENGINEERING; DESIGN ENGINEERING; SYSTEM TESTING;

DATA REDUCTION;

EID: 84948440053     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VTS.2002.1011119     Document Type: Conference Paper

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