Reducing test data volume using LFSR reseeding with seed compression

IEEE International Test Conference (TC)

Volumn , Issue , 2002, Pages 321-330

  Krishna, C V ^a   Touba, Nur A ^a  

^a The University of Texas at Austin   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

AUTOMATIC TESTING; BUILT-IN SELF TEST; DATA COMPRESSION; ENCODING (SYMBOLS); LINEAR EQUATIONS; POLYNOMIALS; SHIFT REGISTERS; STATISTICAL METHODS; VECTORS;

AUTOMATIC TEST EQUIPMENT; LINEAR FEEDBACK SHIFT REGISTER; LOSSLESS TEST VECTOR COMPRESSION; STATISTICAL CODING;

INTEGRATED CIRCUIT TESTING;

EID: 0036446482     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (33)

1. Bardell, P.H., and W.H. McAnney, and J. Savir. Built-in Test for VLSI: Pseudorandom Techniques, John Wiley & Sons, 1987.
2. Bayraktaroglu, L., and A. Ogailoglu, "Test Volume and Application Time Reduction Through Scan Chain Concealment," Proc. of Design Automation Conference, pp. 151-155, 2001.
3. Brglez, F., D. Bryan, and K. Kozminski, "Combinational Profiles of Sequential Benchmark Circuits," Proc. of International Symposium on Circuits and Systems, pp. 1929-1934, 1989.
4. Chandra, A., and K. Chakrabarty, "Test Data Compression for System-on-a-Chip Using Golomb Codes," Proc. of VLSI Test Symposium, pp. 113-120, 2000.
5. Chandra, A., and K. Chakrabarty, "Frequency-Directed Run Length (FDR) Codes with Application to System-on-a-Chip Test Data Compression," Proc. of VLSI Test Symposium, pp. 42-47, 2001.
6. Chen, C.L., "Linear Dependencies in Linear Feedback Shift Registers", IEEE Transactions on Computers, Vol. C-35, No. 12, pp. 1086-1088, Dec. 1986.
7. Cullen, C.G., Linear Algebra with Applications. Addison-Wesley, ISBN 0-673-99386-8, 1997.
8. Das, D., and N.A. Touba, "Reducing Test Data Volume Using External/LBIST Hybrid Test Patterns," Proc. of International Test Conference, pp. 115-122, 2000.
9. Dorsch, R., and H.-J. Wunderlich, "Tailoring ATPG for Embedded Testing," Proc. of International Test Conference, pp. 530-537, 2001.
10. Hamzaoglu, I., and J. Patel, "Test Set Compaction Algorithms for Combinational Circuits," Proc. of International Conference on Computer-Aided Design (ICCAD), pp. 283-289, 1998.
11. Hamzaoglu, I., and J.H. Patel, "Reducing Test Application Time for Full Scan Embedded Cores," Proc. of Int. Symp. on Fault Tolerant Computing, pp. 260-267, 1999.
12. Hellebrand, S., S. Tarnick, J. Rajski, and B. Courtois, "Generation of Vector Patterns Through Reseeding of Multiple-Polynomial Linear Feedback Shift Registers," Proc. of International Test Conference, pp. 120-129, 1992.
13. Hellebrand, S., J. Rajski, S. Tarnick, S. Venkataraman and B. Courtois, "Built-In Test for Circuits with Scan Based on Reseeding of Multiple-Polynomial Linear Feedback Shift Registers," IEEE Transactions on Computers, Vol. 44, No. 2, pp. 223-233, Feb. 1995.
14. Hellebrand, S., B. Reeb, S. Tarnick, and H.-J. Wunderlich, "Pattern Generation for a Deterministic BIST Scheme," Proc. of International Conference on Computer-Aided Design (ICCAD), pp. 88-94, 1995.
15. Hellebrand, S., H.-G. Liang, and H.-J. Wunderlich, "A Mixed Mode BIST Scheme Based on Reseeding of Folding Counters," Proc. of International Test Conference, pp. 778-784, 2000.
16. Huffman, D.A., "A Method for the Construction of Minimum Redundancy Codes," Proc. of IRE, Vol. 40, No. 9, pp. 1098-1101, Sep. 1952.
17. Jas, A., and N.A. Touba, "Test Vector Decompression Via Cyclical Scan Chains and Its Application to Testing Core-Based Designs", Proc. of IEEE International Test Conference, pp. 458-464, 1998.
18. Jas, A., J. Ghosh-Dastidar, and N.A. Touba, "Scan Vector Compression/Decompression Using Statistical Coding", Proc. of IEEE VLSI Test Symposium, pp. 114-120, 1999.
19. Jas, A., and N.A. Touba, "Virtual Scan Chains: A Means for reducing Scan Length in Cores", Proc. of IEEE VLSI Test Symposium, pp. 73-78, 2000.
20. Khoche, A., and J. Rivoir, "I/O Bandwidth Bottleneck for Test: Is it Real?," Proc. of International Workshop on Test Resource Partitioning, 2000.
21. Khoche, A., E. Volkerink, J. Rivoir, and S. Mitra, "Test Vector Compression Using EDA-ATE Synergies," Proc. of IEEE VLSI Test Symposium, pp. 97-102, 2002.
22. Krishna, C.V., A. Jas, and N.A. Touba, "Test Vector Encoding Using Partial LFSR Reseeding", Proc. of IEEE International Test Conference, pp. 885-893, 2001.
23. Könemann, B., "LFSR-Coded Test Patterns for Scan Designs," Proc. of European Test Conference, pp. 237-242, 1991.
24. Könemann, B., "Logic DFT and Test Resource Partitioning for 100M Gate ASICs," Proc. of International Workshop on Test Resource Partitioning, 2000.
25. Krasniewski, A., and S. Pilarski, "Circular Self-Test Path: A Low-Cost BIST Technique for VLSI Circuits," IEEE Trans. on Computer-Aided Design, Vol. 8, No. 1, pp. 46-55, Jan. 1989.
26. Liang, H.-G., S. Hellebrand, and H.-J. Wunderlich, "Two-Dimensional Test Data Compression for Scan-Based Deterministic BIST," Proc. of International Test Conference, pp. 894-902, 2001.
27. Rajski, J., J. Tyszer, and N. Zacharia, "Test Data Decompression for Multiple Scan Designs with Boundary Scan", IEEE Transactions on Computers, Vol. 47, No. 11, pp. 1188-1200, Nov. 1998.
28. Rajski, J., N. Tamarapalli, and J. Tyszer, "Automated Synthesis of Large Phase Shifters for Built-In Self-Test", Proc. of Int. Test Conf., pp. 1047-1056, 1998.
29. Reddy, S.M., K. Miyase, S. Kalihara, and I. Pomeranz, "On Test Data Volume Reduction for Multiple Scan Chain Design," Proc. of IEEE VLSI Test Symposium, pp. 103-108, 2002.
30. Stroud, C.E., "Automated BIST for Sequential Logic Synthesis," IEEE Design & Test, pp. 22-32, Dec. 1988.
31. Venkataramann, S., J. Rajski, S. Hellebrand, and S. Tarnick, "An Efficient BIST Scheme Based on Reseeding of Multiple Polynomial Linear Feedback Shift Registers," Proc. of International Conference on Computer-Aided Design (ICCAD), pp. 572-577, 1993.
32. Zacharia, N., J. Rajski, and J. Tyszer, "Decompression of Test Data Using Variable-Length Seed LFSRs," Proc. of VLSI Test Symp., pp. 426-433, 1995.
33. Zacharia, N., J. Rajski, J. Tyszer, and J. Waicukauski "Two Dimensional Test Data Decompressor for Multiple Scan Designs," Proc. of International Test Conference, pp. 186-194, 1996.