Efficient seed utilization for reseeding based compression [logic testing]

Proceedings of the IEEE VLSI Test Symposium

Volumn 2003-January, Issue , 2003, Pages 232-237

  Volkerink, E H ^a,b   Mitra, S ^c  

^a Stanford University   (United States)

^b AGILENT LABORATORIES   (United States)

^c INTEL CORPORATION   (United States)

Author keywords

Automatic test pattern generation; Bandwidth; Cyclic redundancy check; Flip flops; Hardware; Laboratories; Linear feedback shift registers; Test data compression; Test pattern generators; Testing

Indexed keywords

BANDWIDTH; BANDWIDTH COMPRESSION; COMPUTER HARDWARE; DATA COMPRESSION; FLIP FLOP CIRCUITS; INTEGRATED CIRCUIT TESTING; LABORATORIES; PHASE SHIFT; SHIFT REGISTERS; TESTING;

CYCLIC REDUNDANCY CHECK; LFSR-RESEEDING; LINEAR FEEDBACK SHIFT REGISTERS; MULTIPLE SEEDS; MULTIPLE TEST; TEST APPLICATION TIME; TEST DATA COMPRESSION; TEST PATTERN GENERATOR;

AUTOMATIC TEST PATTERN GENERATION;

EID: 84943519736     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VTEST.2003.1197656     Document Type: Conference Paper

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