메뉴 건너뛰기




Volumn 6, Issue 3, 1998, Pages 464-474

Wave-pipelining: A tutorial and research survey

Author keywords

Performance optimization; VLSI circuits; Wave pipelining

Indexed keywords

COMPUTER AIDED DESIGN; COMPUTER ARCHITECTURE; INTEGRATED CIRCUIT LAYOUT; MICROPROCESSOR CHIPS; OPTIMAL CONTROL SYSTEMS; PIPELINE PROCESSING SYSTEMS;

EID: 0032164772     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/92.711317     Document Type: Review
Times cited : (192)

References (44)
  • 2
    • 33747763957 scopus 로고
    • Today's microprocessor aim for flexibility
    • P. Bannon and A. Jan, "Today's microprocessor aim for flexibility," EE Times, pp. 68-70, 1994.
    • (1994) EE Times , pp. 68-70
    • Bannon, P.1    Jan, A.2
  • 10
    • 84889152211 scopus 로고
    • Design and realization of high-performance wave-pipelined 8 × 8 b multiplier in CMOS technology
    • D. Ghosh and S. Nandy, "Design and realization of high-performance wave-pipelined 8 × 8 b multiplier in CMOS technology," IEEE Trans. VLSI Syst., vol. 3, pp. 37-48, 1995.
    • (1995) IEEE Trans. VLSI Syst. , vol.3 , pp. 37-48
    • Ghosh, D.1    Nandy, S.2
  • 13
    • 0028388471 scopus 로고
    • A sampling technique and its CMOS implementation with 1 Gb/s bandwidth and 25 ps resolution
    • Mar.
    • C. Gray, W. Liu, W. van Noije, T. Hughes, and R. Cavin, "A sampling technique and its CMOS implementation with 1 Gb/s bandwidth and 25 ps resolution," IEEE J. Solid-State Circuits, pp. 340-349, Mar. 1994.
    • (1994) IEEE J. Solid-State Circuits , pp. 340-349
    • Gray, C.1    Liu, W.2    Van Noije, W.3    Hughes, T.4    Cavin, R.5
  • 14
    • 33747796234 scopus 로고
    • private communication, Nov.
    • S. Gupta, private communication, Nov. 1994.
    • (1994)
    • Gupta, S.1
  • 15
    • 33747757144 scopus 로고
    • A 300 MHz 4-mb wave-pipelined CMOS SRAM using a multi-phase PLL
    • K. Ishibashi et al., "A 300 MHz 4-mb wave-pipelined CMOS SRAM using a multi-phase PLL," in Proc. ISSCC'95, 1995, pp. 308-309.
    • (1995) Proc. ISSCC'95 , pp. 308-309
    • Ishibashi, K.1
  • 16
    • 0026174905 scopus 로고
    • Placement for clock period minimization with multiple wave propagation
    • D. A. Joy and M. J. Ciesielski, "Placement for clock period minimization with multiple wave propagation," in Proc. 28th Design Automation Conf., 1991.
    • (1991) Proc. 28th Design Automation Conf.
    • Joy, D.A.1    Ciesielski, M.J.2
  • 18
    • 33747806571 scopus 로고
    • A high speed multiplier design using wave pipelining technique
    • Australia
    • S. T. Ju and C. W. Jen, "A high speed multiplier design using wave pipelining technique," in Proc. IEEE APCCAS, Australia, 1992, pp. 502-506.
    • (1992) Proc. IEEE APCCAS , pp. 502-506
    • Ju, S.T.1    Jen, C.W.2
  • 19
    • 0028055471 scopus 로고
    • A monolithic 625 mb/s data recovery circuit in 1.2 μm CMOS
    • J. Kang, W. Liu, and R. Cavin, "A monolithic 625 mb/s data recovery circuit in 1.2 μm CMOS," in Proc. Custom Integrated Circuit Conf., 1993, pp. 625-628.
    • (1993) Proc. Custom Integrated Circuit Conf. , pp. 625-628
    • Kang, J.1    Liu, W.2    Cavin, R.3
  • 25
    • 84865918222 scopus 로고
    • PA-RISC processor for "Snake" work-stations
    • C. Kohlhardt, "PA-RISC processor for "Snake" work-stations," in Hot Chips Symp., 1991, pp. 1.20-1.31.
    • (1991) Hot Chips Symp.
    • Kohlhardt, C.1
  • 29
    • 0027880690 scopus 로고
    • The practical application of retiming to the design of high-performance systems
    • B. Lockyear and C. Ebeling, "The practical application of retiming to the design of high-performance systems," in Proc. ICCAD'93, 1993, pp. 288-295.
    • (1993) Proc. ICCAD'93 , pp. 288-295
    • Lockyear, B.1    Ebeling, C.2
  • 30
    • 5244234489 scopus 로고
    • A technique for high-speed, fine-resolution pattern generation and its CMOS implementation
    • G. Moyer, M. Clements, W. Liu, T. Schaffer, and R. Cavin, "A technique for high-speed, fine-resolution pattern generation and its CMOS implementation," in Proc. 16th Conf. Advanced Res. VLSI, 1995, pp. 131-145.
    • (1995) Proc. 16th Conf. Advanced Res. VLSI , pp. 131-145
    • Moyer, G.1    Clements, M.2    Liu, W.3    Schaffer, T.4    Cavin, R.5
  • 31
    • 0028545963 scopus 로고
    • A 220-MHz pipelined 16-mb BiCMOS SRAM with PLL proportional self-timing generator
    • Nov.
    • K. Nakamura et al., "A 220-MHz pipelined 16-mb BiCMOS SRAM with PLL proportional self-timing generator," IEEE J. Solid-State Circuits, pp. 1317-1322, Nov. 1994.
    • (1994) IEEE J. Solid-State Circuits , pp. 1317-1322
    • Nakamura, K.1
  • 33
    • 0029178563 scopus 로고
    • System design using wave-pipelining: A CMOS VLSI vector unit
    • K. Nowka and M. Flynn, "System design using wave-pipelining: A CMOS VLSI vector unit," in Proc. ISCAS'95, 1995, pp. 2301-2304.
    • (1995) Proc. ISCAS'95 , pp. 2301-2304
    • Nowka, K.1    Flynn, M.2
  • 34
    • 0343168930 scopus 로고
    • Delay synchronization in time-of-flight optical systems
    • J. Pratt and V. Heuring, "Delay synchronization in time-of-flight optical systems," Appl. Opt., vol. 31, no. 14, pp. 2430-2437, 1992.
    • (1992) Appl. Opt. , vol.31 , Issue.14 , pp. 2430-2437
    • Pratt, J.1    Heuring, V.2
  • 35
    • 33747754718 scopus 로고
    • The design and implementation of a very fast experimental pipelining computer
    • L. Qi and X. Peisu, "The design and implementation of a very fast experimental pipelining computer," J. Comput. Sci. Technol., vol. 2, no. 1, pp. 1-6, 1988.
    • (1988) J. Comput. Sci. Technol. , vol.2 , Issue.1 , pp. 1-6
    • Qi, L.1    Peisu, X.2
  • 40
    • 0029291571 scopus 로고
    • A 2.6 ns wavepipelined CMOS SRAM with dueal-sensing-latch circuits
    • Apr.
    • S. Tachibana et al., "A 2.6 ns wavepipelined CMOS SRAM with dueal-sensing-latch circuits," IEEE J. Solid-State Circuits, pp. 487-490, Apr. 1995.
    • (1995) IEEE J. Solid-State Circuits , pp. 487-490
    • Tachibana, S.1
  • 42
    • 0026869432 scopus 로고
    • A bipolar population counter using wave pipelining to achieve 2.5x normal clock frequency
    • May
    • D. Wong, G. De Micheli, M. Flynn, and R. Huston, "A bipolar population counter using wave pipelining to achieve 2.5x normal clock frequency," IEEE J. Solid-State Circuits, vol. 27, May 1992.
    • (1992) IEEE J. Solid-State Circuits , vol.27
    • Wong, D.1    De Micheli, G.2    Flynn, M.3    Huston, R.4
  • 43
    • 4143052654 scopus 로고
    • Designing high performance digital circuits using wave pipelining: Algorithms and practical experiences
    • Jan.
    • D. Wong, G. De Micheli, and M. Flynn, "Designing high performance digital circuits using wave pipelining: Algorithms and practical experiences," IEEE Trans. Computer-Aided Design, vol. 12, Jan. 1993.
    • (1993) IEEE Trans. Computer-Aided Design , vol.12
    • Wong, D.1    De Micheli, G.2    Flynn, M.3
  • 44
    • 0008690193 scopus 로고
    • A 150 MHz 8-banks 256 in synchronous DRAM with wave pipelining methods
    • H. Yoo et al., "A 150 MHz 8-banks 256 in synchronous DRAM with wave pipelining methods," in Proc. ISSCC'95, 1995, pp. 250-251.
    • (1995) Proc. ISSCC'95 , pp. 250-251
    • Yoo, H.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.