Conditional pre-charge techniques for power-efficient dual-edge clocking

Proceedings of the International Symposium on Low Power Electronics and Design, Digest of Technical Papers

Volumn , Issue , 2002, Pages 56-59

  Nedovic, Nikola ^a   Aleksic, Marko ^a   Oklobdzija, Vojin G ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

Clock distribution; Clocked storage elements; Clocking; Dual edge triggered flip flop; Power consumption

Indexed keywords

COMPUTER SIMULATION; FLIP FLOP CIRCUITS; LOGIC DESIGN; SEQUENTIAL CIRCUITS;

CONDITIONAL PRE-CHARGING TECHNIQUES; POWER-EFFICIENT DUAL-EDGE CLOCKING;

TIMING CIRCUITS;

EID: 0036949327     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/lpe.2002.146709     Document Type: Conference Paper

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