Design and optimization of sense-amplifier-based flip-flops

European Solid-State Circuits Conference

Volumn , Issue , 1999, Pages 410-413

  Nikolić, Borivoje ^a   Oklobdžija, Vojin G ^b  

^a University of California   (United States)

^b Integration Corporation   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS TECHNOLOGY; DESIGN AND OPTIMIZATION; FLOATING NODES; IMPROVED DESIGNS;

CMOS INTEGRATED CIRCUITS; DESIGN;

FLIP FLOP CIRCUITS;

EID: 0037549815     PISSN: 19308833     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. M. Matsui et al. "A 200MHz 13mm2 2-D DCT Macrocell Using Sense-Amplifying Pipeline Flip-Flop Scheme, " IEEE Journal of Solid-State Circuits, vol. 29, no. 12, pp. 1482-1490, Dec. 1994.
2. D. Dobberpuhl, "The Design of a High Performance Low Power Microprocessor, " Proceedings International Symposium on Low-Power Electronics and Design, August 1996.
3. B. Nikolic, V. Stojanovic, V.G. Oklobdzija, W. Jia, J. Chiu, M. Leung, "Sense Amplifier-Based Flip-Flop, " 1999. International Solid-State Circuits Conference, Digest of Technical Papers, ISSCC'99 February 1999.
4. F. Klass, "Semi-Dynamic and Dynamic Flip-Flops with Embedded Logic, " Symposium on VLSI Circuits, Digest of Technical Papers, June 1998.
5. V. Stojanovic, V.G. Oklobdzija, "Comparative Analysis of Master-Slave Latches and Flip-Flops for High-Performance and Low-Power Systems, " IEEE Journal of Solid-State Circuits, vol. 34, no. 4, pp. 536548, April 1999.