Concurrent Application of Compaction and Compression for Test Time and Data Volume Reduction in Scan Designs

IEEE Transactions on Computers

Volumn 52, Issue 11, 2003, Pages 1480-1489

  Bayraktaroglu, Ismet ^a   Orailoglu, Alex ^b  

^a SUN MICROSYSTEMS   (United States)

^b UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

Deterministic decompression; On chip decompression; Scan chains; Test pattern compaction; Test pattern compression

Indexed keywords

COMPUTER HARDWARE; COMPUTER SIMULATION; VECTORS; VIRTUAL REALITY;

SCAN CHAINS; TEST PATTERN COMPRESSION;

DATA COMPRESSION;

EID: 0242412947     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/TC.2003.1244945     Document Type: Article

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