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Volumn , Issue , 1997, Pages 300-305

Test compaction in a parallel access scan environment

Author keywords

[No Author keywords available]

Indexed keywords

PARALLEL ACCESS SCAN; TEST COMPACTION;

EID: 0031355488     PISSN: 10817735     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (8)

References (15)
  • 2
    • 0018809498 scopus 로고
    • Test generation and dynamic compaction of tests
    • P.Goel and B.C.Rosales, Test Generation and Dynamic Compaction of Tests, ITC 1979, pp.189-192.
    • (1979) ITC , pp. 189-192
    • Goel, P.1    Rosales, B.C.2
  • 3
    • 0026618720 scopus 로고
    • COMPACTEST: A method to generate compact test sets for combinational circuits
    • I.Pomeranz et al, COMPACTEST: A Method to Generate Compact Test Sets for Combinational Circuits, ITC 1991, pp. 194-203.
    • (1991) ITC , pp. 194-203
    • Pomeranz, I.1
  • 4
    • 84895163431 scopus 로고
    • A Design for testability scheme to reduce test application time
    • D.K.Pradhan and J.Saxena, A Design For Testability Scheme to Reduce Test Application Time, VTS 1992, pp. 55-60.
    • (1992) VTS , pp. 55-60
    • Pradhan, D.K.1    Saxena, J.2
  • 5
    • 0026962995 scopus 로고
    • An algorithm to reduce test application time in full scan designs
    • S.Lee and K.Saluja, An Algorithm to Reduce Test Application Time in Full Scan Designs, ICCAD 1992, pp. 1720.
    • (1992) ICCAD , pp. 1720
    • Lee, S.1    Saluja, K.2
  • 6
    • 0026999280 scopus 로고
    • Configuring multiple scan chains for minimum test time
    • S.Narayan et al., Configuring Multiple Scan Chains for Minimum Test Time, ICCAD 1992, pp. 4-8.
    • (1992) ICCAD , pp. 4-8
    • Narayan, S.1
  • 7
    • 0025481029 scopus 로고
    • ATPG for ultra-large structured designs
    • J.Waicukauski et al., ATPG for Ultra-Large Structured Designs, ITC 1990, pp. 44-51.
    • (1990) ITC , pp. 44-51
    • Waicukauski, J.1
  • 8
    • 0026741375 scopus 로고
    • Selectable length partial scan: A method to reduce vector length
    • S.Morley and R.Marlett, Selectable Length Partial Scan: A Method to Reduce Vector Length, ITC 1991, pp. 385-392.
    • (1991) ITC , pp. 385-392
    • Morley, S.1    Marlett, R.2
  • 9
    • 0024177231 scopus 로고
    • Compaction of ATPG-generated test sequences for sequential circuits
    • R. K. Roy et al., Compaction of ATPG-generated test sequences for sequential circuits, ICCAD, pp. 382-385, 1988.
    • (1988) ICCAD , pp. 382-385
    • Roy, R.K.1
  • 10
    • 0026817739 scopus 로고
    • Test compaction for sequential circuits
    • Feb
    • T. M. Niermann et al., Test compaction for sequential circuits, IEEE Trans. Computer-Aided Design, vol. 11, pp. 260-267, Feb. 1992.
    • (1992) IEEE Trans. Computer-Aided Design , vol.11 , pp. 260-267
    • Niermann, T.M.1
  • 11
    • 84895089957 scopus 로고    scopus 로고
    • A Unifying methodology for intellectual property and custom logic testing
    • S.Bhatia et al., A Unifying Methodology for Intellectual Property and Custom Logic Testing, ITC 1996, pp. 639648.
    • (1996) ITC , pp. 639648
    • Bhatia, S.1
  • 12
    • 0018996451 scopus 로고
    • Testing VLSI with random access scan
    • H. Ando, Testing VLSI with Random Access Scan, COM-PCON 1980, pp. 50-52.
    • (1980) COM-PCON , pp. 50-52
    • Ando, H.1
  • 14
    • 0026175482 scopus 로고
    • ATPG based on a novel grid addressable latch element
    • S. Chandra et al., ATPG Based on a Novel Grid Addressable Latch Element, DAC 1991, pp. 282-286.
    • (1991) DAC , pp. 282-286
    • Chandra, S.1
  • 15
    • 0029512009 scopus 로고
    • Structured design-for-debug-the supersparc ii methodology and implementation
    • H. Hao & R. Avrà, Structured Design-For-Debug-the SuperSparc II Methodology and Implementation, ITC 1995, pp. 175-183.
    • (1995) ITC , pp. 175-183
    • Hao, H.1    Avrà, R.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.