Static test compaction for scan-based designs to reduce test application time

Proceedings of the Asian Test Symposium

Volumn , Issue , 1998, Pages 198-203

  Pomeranz, Irith ^a   Reddy, Sudhakar M ^a  

^a UNIVERSITY OF IOWA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

STATIC TEST COMPACTION;

ELECTRON DEVICE TESTING; LOGIC DESIGN;

SEQUENTIAL CIRCUITS;

EID: 0032298005     PISSN: 10817735     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (15)

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3. S. Y. Lee and K. K. Saluja, "An Algorithm to Reduce Test Application Time in Full Scan Designs", in Proc. 1992 Intl. Conf. on Computer-Aided Design, Nov. 1992, pp. 17-20.
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