Reducing test application time for Built-in-Self-Test test pattern generators

Proceedings of the IEEE VLSI Test Symposium

Volumn , Issue , 2000, Pages 369-375

  Hamzaoglu, Ilker ^a   Patel, Janak H ^a  

^a MOTOROLA INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; BENCHMARKING; BUILT-IN SELF TEST; COMBINATORIAL CIRCUITS; COUNTING CIRCUITS; FAILURE ANALYSIS;

AUTOMATIC TEST PATTERN GENERATOR; BINARY COUNTER; C-COMPATIBILITY TECHNIQUE; STUCK-AT-FAULT COVERAGE;

INTEGRATED CIRCUIT TESTING;

EID: 0033733145     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Article

References (20)