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Volumn , Issue , 2003, Pages 1135-1144

A Reconfigurable Power-Conscious Core Wrapper and its Application to SOC Test Scheduling

Author keywords

[No Author keywords available]

Indexed keywords

AUTOMATIC TESTING; ELECTRIC POWER SUPPLIES TO APPARATUS; ENERGY DISSIPATION; INTEGER PROGRAMMING; LINEAR PROGRAMMING; SCHEDULING;

EID: 0142215922     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (27)

References (24)
  • 2
    • 84891459569 scopus 로고    scopus 로고
    • Springer-Verlag, ISBN 3-540-64105-X
    • P. Brucker, "Scheduling Algorithms", Springer-Verlag, ISBN 3-540-64105-X, 1998.
    • (1998) Scheduling Algorithms
    • Brucker, P.1
  • 4
    • 0031163752 scopus 로고    scopus 로고
    • Scheduling Tests for VLSI Systems under Power Constraints
    • June
    • R. Chou, K. Saluja, and V. Agrawal, "Scheduling Tests for VLSI Systems under Power Constraints", Transactions on VLSI Systems, Vol. 5, No. 2, pp. 175-185, June 1997.
    • (1997) Transactions on VLSI Systems , vol.5 , Issue.2 , pp. 175-185
    • Chou, R.1    Saluja, K.2    Agrawal, V.3
  • 7
    • 2542506028 scopus 로고    scopus 로고
    • A Novel Test Time Reduction Algorithm for Test Architecture Design for core-Based System Chips
    • Corfu, Greece, May
    • S. K. Goel and E.J. Marinissen, "A Novel Test Time Reduction Algorithm for Test Architecture Design for core-Based System Chips", Digest of papers European Test Workshop (ETW), pp 41-46, Corfu, Greece, May 2002.
    • (2002) Digest of Papers European Test Workshop (ETW) , pp. 41-46
    • Goel, S.K.1    Marinissen, E.J.2
  • 8
    • 0002515893 scopus 로고    scopus 로고
    • Cluster-Based Test Architecture Design for System-On-Chip
    • Monterey, California, April
    • S. K. Goel and E. J. Marinissen, "Cluster-Based Test Architecture Design for System-On-Chip, Proceedings of VLSI Test Symposium (VTS), pp. 259-264, Monterey, California, April 2002.
    • (2002) Proceedings of VLSI Test Symposium (VTS) , pp. 259-264
    • Goel, S.K.1    Marinissen, E.J.2
  • 11
    • 0036047771 scopus 로고    scopus 로고
    • Wrapper/ TAM Co-Optimization, Constraint-Driven Test Scheduling, and Test Data Volume Reduction for SOCs
    • New Orleans, Louisiana, June
    • V. Iyengar, K. Chakrabarty, and E. J. Marinissen, "Wrapper/ TAM Co-Optimization, Constraint-Driven Test Scheduling, and Test Data Volume Reduction for SOCs", Proceedings of IEEE/ACM Design Automation Conference (DAC), pp. 685690, New Orleans, Louisiana, June 2002.
    • (2002) Proceedings of IEEE/ACM Design Automation Conference (DAC) , pp. 685-690
    • Iyengar, V.1    Chakrabarty, K.2    Marinissen, E.J.3
  • 14
  • 15
    • 0036694332 scopus 로고    scopus 로고
    • A Novel Reconfigurable Wrapper for Testing Embedded Core-Based and its Associated Scheduling
    • August
    • S. Koranne, "A Novel Reconfigurable Wrapper for Testing Embedded Core-Based and its Associated Scheduling", Journal of Electronic Testing; Theory and Applications (JETTA), pp. 415-434, August 2002.
    • (2002) Journal of Electronic Testing; Theory and Applications (JETTA) , pp. 415-434
    • Koranne, S.1
  • 21
    • 0034479808 scopus 로고    scopus 로고
    • Power Conscious Test Synthesis and Scheduling for BIST RTL Data Paths
    • Atlantic City, NJ, Oct.
    • N. Nicolici and B. M. Al-Hashimi, "Power Conscious Test Synthesis and Scheduling for BIST RTL Data Paths", Proceedings of International Test Conference (ITC), pp. 662-671, Atlantic City, NJ, Oct. 2000.
    • (2000) Proceedings of International Test Conference (ITC) , pp. 662-671
    • Nicolici, N.1    Al-Hashimi, B.M.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.