Scan architecture for shift and capture cycle power reduction

Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

Volumn 2002-January, Issue , 2002, Pages 129-137

  Rosinger, P M ^a   Al Hashimi, B M ^a   Nicolici, N ^b  

^a UNIVERSITY OF SOUTHAMPTON   (United Kingdom)

^b MCMASTER UNIVERSITY   (Canada)

Author keywords

Circuit testing; Clocks; Controllability; Digital integrated circuits; Integrated circuit testing; Integrated circuit yield; Logic circuits; Observability; Power dissipation; Switching circuits

Indexed keywords

BUILT-IN SELF TEST; CHAINS; CHOPPERS (CIRCUITS); CLOCKS; CONSTRAINT SATISFACTION PROBLEMS; CONTROLLABILITY; DEFECTS; DESIGN FOR TESTABILITY; DIGITAL INTEGRATED CIRCUITS; ELECTRIC POWER SUPPLIES TO APPARATUS; ENERGY DISSIPATION; FAULT TOLERANCE; INTEGRATED CIRCUIT TESTING; INTEGRATED CIRCUITS; LOGIC CIRCUITS; OBSERVABILITY; SWITCHING CIRCUITS; VLSI CIRCUITS;

CIRCUIT TESTING; CIRCUIT UNDER TEST; DESTRUCTIVE TESTS; LOW POWER DESIGN TECHNIQUE; SCAN ARCHITECTURE; SCAN CHAIN PARTITIONING; SWITCHING ACTIVITIES; UNIFIED SOLUTIONS;

ELECTRIC LOSSES;

EID: 17644392010     PISSN: 15505774     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DFTVS.2002.1173509     Document Type: Conference Paper

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