Power conscious test synthesis and scheduling for BIST RTL data paths

IEEE International Test Conference (TC)

Volumn , Issue , 2000, Pages 662-671

  Nicolici, Nicola ^a   Al Hashimi, Bashir M ^a  

^a UNIVERSITY OF SOUTHAMPTON   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTER WORKSTATIONS; INTEGRATED CIRCUIT TESTING; SHIFT REGISTERS; VLSI CIRCUITS;

POWER CONSCIOUS TEST SYNTHESIS AND SCHEDULING; REGISTER TRANSFER LEVEL;

BUILT-IN SELF TEST;

EID: 0034479808     PISSN: 10893539     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

References (40)