-
2
-
-
0020830319
-
Threshold voltage of thin-film silicon-on-insulator (SOI) MOSFETs
-
Oct.
-
H.-K. Lim and J. G. Fossum, "Threshold voltage of thin-film silicon-on-insulator (SOI) MOSFETs," IEEE Trans. Electron Devices, vol. ED-30, pp. 1244-1251, Oct. 1983.
-
(1983)
IEEE Trans. Electron Devices
, vol.ED-30
, pp. 1244-1251
-
-
Lim, H.-K.1
Fossum, J.G.2
-
3
-
-
84948591734
-
Performance limitation of deep-submicron fully depleted SOI MOSFETs
-
J. G. Fossum, S. Krishnan, and P.-C. Yeh, "Performance limitation of deep-submicron fully depleted SOI MOSFETs," in Proc. IEEE Int. SOI Conf., Oct. 1992, pp. 132-133.
-
Proc. IEEE Int. SOI Conf., Oct. 1992
, pp. 132-133
-
-
Fossum, J.G.1
Krishnan, S.2
Yeh, P.-C.3
-
4
-
-
0141967569
-
-
San Jose, CA: Semiconductor Industry Association
-
Int. Tech. Roadmap Semicond. (ITRS). San Jose, CA: Semiconductor Industry Association, 2001.
-
(2001)
Int. Tech. Roadmap Semicond. (ITRS)
-
-
-
5
-
-
33646900503
-
Device scaling limits of Si MOSFETs and their application dependencies
-
Mar.
-
D. J. Frank et al., "Device scaling limits of Si MOSFETs and their application dependencies," Proc. IEEE, vol. 89, pp. 259-288, Mar. 2001.
-
(2001)
Proc. IEEE
, vol.89
, pp. 259-288
-
-
Frank, D.J.1
-
6
-
-
85056911965
-
Monte Carlo simulation of a 30nm dual-gate MOSFET: How short can Si go?
-
Dec.
-
D. J. Frank, S. E. Laux, and M. V. Fischetti, "Monte Carlo simulation of a 30nm dual-gate MOSFET: How short can Si go?," in IEDM Tech. Dig., Dec. 1992, pp. 553-556.
-
(1992)
IEDM Tech. Dig.
, pp. 553-556
-
-
Frank, D.J.1
Laux, S.E.2
Fischetti, M.V.3
-
7
-
-
0035717886
-
Examination of design and manufacturing issues in a 10 nm double gate MOSFET using nonequilibrium Greens function simulation
-
Dec
-
Z. Ren et al., "Examination of design and manufacturing issues in a 10 nm double gate MOSFET using nonequilibrium Greens function simulation," in IEDM Tech. Dig., Dec 2001, pp. 107-110.
-
(2001)
IEDM Tech. Dig.
, pp. 107-110
-
-
Ren, Z.1
-
8
-
-
0035250378
-
Double-gate CMOS: Symmetrical-versus asymmetrical-gate devices
-
Feb.
-
K. Kim and J. G. Fossum, "Double-gate CMOS: Symmetrical-versus asymmetrical-gate devices," IEEE Trans. Electron Devices, vol. 48, pp. 294-299, Feb. 2001.
-
(2001)
IEEE Trans. Electron Devices
, vol.48
, pp. 294-299
-
-
Kim, K.1
Fossum, J.G.2
-
9
-
-
0036053770
-
35nm CMOS FinFETs
-
June
-
F.-L. Yang et al., "35nm CMOS FinFETs," in Symp. VLSI Tech. Dig., June 2002, pp. 104-105.
-
(2002)
Symp. VLSI Tech. Dig.
, pp. 104-105
-
-
Yang, F.-L.1
-
10
-
-
0033900449
-
Highly suppressed short-channel effects in ultrathin SOI n-MOSFETs
-
Feb.
-
E. Suzuki et al., "Highly suppressed short-channel effects in ultrathin SOI n-MOSFETs," IEEE Trans. Electron Devices, vol. 47, pp. 354-359, Feb. 2000.
-
(2000)
IEEE Trans. Electron Devices
, vol.47
, pp. 354-359
-
-
Suzuki, E.1
-
11
-
-
0033750493
-
Ultrathin-body SOI MOSFET for deep-sub-tenth micron era
-
May
-
Y.-K. Choi et al., "Ultrathin-body SOI MOSFET for deep-sub-tenth micron era," IEEE Electron Device Lett., vol. 21, pp. 254-256, May 2000.
-
(2000)
IEEE Electron Device Lett.
, vol.21
, pp. 254-256
-
-
Choi, Y.-K.1
-
12
-
-
0036923554
-
Extreme scaling with ultrathin Si channel MOSFETs
-
Dec
-
B. Doris, et al., "Extreme scaling with ultrathin Si channel MOSFETs," in IEDM Tech. Dig., Dec 2002, pp. 267-270.
-
(2002)
IEDM Tech. Dig.
, pp. 267-270
-
-
Doris, B.1
-
13
-
-
18344401509
-
A 50nm depleted-substrate CMOS transistor (DST)
-
Dec
-
R. Chau et al., "A 50nm depleted-substrate CMOS transistor (DST)," in IEDM Tech. Dig., Dec 2001, pp. 621-6232.
-
(2001)
IEDM Tech. Dig.
, pp. 621-6232
-
-
Chau, R.1
-
14
-
-
0036475197
-
Analytical modeling of quantization and volume inversion in thin Si-film double-gate MOSFETs
-
Feb.
-
L. Ge and J. G. Fossum, "Analytical modeling of quantization and volume inversion in thin Si-film double-gate MOSFETs," IEEE Trans. Electron Devices, vol. 49, pp. 287-294, Feb. 2002.
-
(2002)
IEEE Trans. Electron Devices
, vol.49
, pp. 287-294
-
-
Ge, L.1
Fossum, J.G.2
-
15
-
-
0032072525
-
Monte Carlo simulation of electron transport properties in extremely thin SOI MOSFETs
-
May
-
F. Gámiz et al., "Monte Carlo simulation of electron transport properties in extremely thin SOI MOSFETs," IEEE Trans. Electron Devices, vol. 45, pp. 1122-1126, May 1998.
-
(1998)
IEEE Trans. Electron Devices
, vol.45
, pp. 1122-1126
-
-
Gámiz, F.1
-
16
-
-
3242844030
-
Electron mobility in extremely thin single-gate silicon-on-insulator inversion layers
-
Dec
-
____, "Electron mobility in extremely thin single-gate silicon-on-insulator inversion layers," J. Appl. Phys., vol. 86, no. 11, pp. 6269-6275, Dec 1999.
-
(1999)
J. Appl. Phys.
, vol.86
, Issue.11
, pp. 6269-6275
-
-
Gámiz, F.1
-
17
-
-
0035696689
-
Low field electron and hole mobility of SOI transistors fabricated on ultrathin silicon films for deep submicrometer technology applications
-
Dec.
-
D. Esseni et al., "Low field electron and hole mobility of SOI transistors fabricated on ultrathin silicon films for deep submicrometer technology applications," IEEE Trans. Electron Devices, vol. 48, pp. 2842-2850, Dec. 2001.
-
(2001)
IEEE Trans. Electron Devices
, vol.48
, pp. 2842-2850
-
-
Esseni, D.1
-
18
-
-
0029379215
-
Physical subthreshold MOSFET modeling applied to viable design of deep-submicrometer fully-depleted SOI low-voltage CMOS technology
-
Sept.
-
P. C. Yeh and J. G. Fossum, "Physical subthreshold MOSFET modeling applied to viable design of deep-submicrometer fully-depleted SOI low-voltage CMOS technology," IEEE Trans. Electron Devices, vol. 42, pp. 1605-1613, Sept. 1995.
-
(1995)
IEEE Trans. Electron Devices
, vol.42
, pp. 1605-1613
-
-
Yeh, P.C.1
Fossum, J.G.2
-
19
-
-
0036454688
-
Device design for subthreshold slope and threshold voltage control in sub-100nm fully-depleted SOI MOSFETs
-
T. Numata et al., "Device design for subthreshold slope and threshold voltage control in sub-100nm fully-depleted SOI MOSFETs," in Proc. IEEE Int. SOI Conf., Oct. 2002, pp. 179-180.
-
Proc. IEEE Int. SOI Conf., Oct. 2002
, pp. 179-180
-
-
Numata, T.1
-
20
-
-
0024106969
-
A physical short-channel model for the thin-film SOI MOSFET applicable to device and circuit CAD
-
Nov.
-
S. Veeraraghavan and J. G. Fossum, "A physical short-channel model for the thin-film SOI MOSFET applicable to device and circuit CAD," IEEE Trans. Electron Devices, vol. 25, pp. 1866-1875, Nov. 1988.
-
(1988)
IEEE Trans. Electron Devices
, vol.25
, pp. 1866-1875
-
-
Veeraraghavan, S.1
Fossum, J.G.2
-
21
-
-
0031383716
-
Design criteria for a fully depleted-0.1 mm SOI technology
-
J. A. Burns et al., "Design criteria for a fully depleted-0.1 mm SOI technology," in Proc. IEEE Int. SOI Conf., Oct. 1997, pp. 78-79.
-
Proc. IEEE Int. SOI Conf., Oct. 1997
, pp. 78-79
-
-
Burns, J.A.1
-
22
-
-
0036454454
-
Scaling assessment of fully-depleted SOI technology at the 30nm gate length generation
-
A. Vandooren et al., "Scaling assessment of fully-depleted SOI technology at the 30nm gate length generation," in Proc. IEEE Int. SOI Conf., Oct. 2002, pp. 25-26.
-
Proc. IEEE Int. SOI Conf., Oct. 2002
, pp. 25-26
-
-
Vandooren, A.1
-
23
-
-
0009754096
-
Design and analyses of double-gate CMOS for low-voltage integrated circuit applications, including physical modeling of silicon-on-insulator MOSFETs
-
Ph.D. dissertation, Univ. of Florida, Gainesville
-
K. Kim, "Design and analyses of double-gate CMOS for low-voltage integrated circuit applications, including physical modeling of silicon-on-insulator MOSFETs," Ph.D. dissertation, Univ. of Florida, Gainesville, 2001.
-
(2001)
-
-
Kim, K.1
-
25
-
-
0141967561
-
-
Fremont, CA: Avant! Corp.
-
MEDICI-4.0 Users Manual. Fremont, CA: Avant! Corp., 1999.
-
(1999)
MEDICI-4.0 Users Manual
-
-
-
27
-
-
0142002292
-
SOI uniformity and surface smoothness processing
-
L. P. Allen et al., "SOI uniformity and surface smoothness processing," in Proc. IEEE Int. SOI Conf., Oct. 2002, pp. 192-193.
-
Proc. IEEE Int. SOI Conf., Oct. 2002
, pp. 192-193
-
-
Allen, L.P.1
-
28
-
-
0033281305
-
Monte Carlo modeling of threshold variation due to dopant fluctuation
-
June
-
D. J. Frank et al., "Monte Carlo modeling of threshold variation due to dopant fluctuation," in Symp. VLSI Tech. Dig., June 1999, pp. 169-170.
-
(1999)
Symp. VLSI Tech. Dig.
, pp. 169-170
-
-
Frank, D.J.1
-
29
-
-
0035446168
-
Physical compact modeling and analyses of velocity overshoot in extremely scaled CMOS devices and circuits
-
Sept.
-
L. Ge, J. G. Fossum, and B. Liu, "Physical compact modeling and analyses of velocity overshoot in extremely scaled CMOS devices and circuits," IEEE Trans. Electron Devices, vol. 48, pp. 2074-2080, Sept. 2001.
-
(2001)
IEEE Trans. Electron Devices
, vol.48
, pp. 2074-2080
-
-
Ge, L.1
Fossum, J.G.2
Liu, B.3
-
30
-
-
0035716658
-
Robust ternary metal gate electrodes for dual gate CMOS devices
-
Dec.
-
D.-G. Park et al., "Robust ternary metal gate electrodes for dual gate CMOS devices," in IEEE IEDM Tech. Dig., Dec. 2001, pp. 671-674.
-
(2001)
IEEE IEDM Tech. Dig.
, pp. 671-674
-
-
Park, D.-G.1
-
31
-
-
0036923594
-
Metal-gate FinFET and fully-depleted SOI devices using total gate silicidation
-
Dec.
-
J. Kedzierski et al., "Metal-gate FinFET and fully-depleted SOI devices using total gate silicidation," in IEDM Tech. Dig., Dec. 2002, pp. 247-250.
-
(2002)
IEDM Tech. Dig.
, pp. 247-250
-
-
Kedzierski, J.1
-
32
-
-
0001588155
-
A process-based compact model for double-gate MOSFETs
-
Mar.
-
M.-H. Chiang and J. G. Fossum, "A process-based compact model for double-gate MOSFETs," in Proc. Int. Symp. SOI Technol. Devices, ECS, vol. 2001-3, Mar. 2001, pp. 421-426.
-
(2001)
Proc. Int. Symp. SOI Technol. Devices, ECS
, vol.3
, pp. 421-426
-
-
Chiang, M.-H.1
Fossum, J.G.2
-
33
-
-
6344252806
-
A physics-based compact model for nano-scale DG and FD/SOI MOSFETs
-
J. G. Fossum, L. Ge, and M.-H. Chiang, "A physics-based compact model for nano-scale DG and FD/SOI MOSFETs," in Proc. Tech. Nanotechnol. Conf., Feb. 2003, pp. 274-277.
-
Proc. Tech. Nanotechnol. Conf., Feb. 2003
, pp. 274-277
-
-
Fossum, J.G.1
Ge, L.2
Chiang, M.-H.3
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