Device design for subthreshold slope and threshold voltage control in sub-100 nm fully-depleted SOI MOSFETs

IEEE International SOI Conference

Volumn , Issue , 2002, Pages 179-180

  Numata, Toshinori ^a   Uchida, Ken ^a   Koga, Junji ^a   Takagi, Shin Ichi ^a  

^a TOSHIBA CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; PERMITTIVITY; SILICON ON INSULATOR TECHNOLOGY; THRESHOLD VOLTAGE; VOLTAGE CONTROL;

SHORT CHANNEL EFFECTS (SCE);

MOSFET DEVICES;

EID: 0036454688     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/soi.2002.1044467     Document Type: Conference Paper

References (3)

1. Y. Omura et al., IEDM Tech. Dig., 1991, pp. 75-678.
2. R. Koh, Jpn. J. Appl. Phys., pp. 2294-2299, 1999.
3. M. Takamiya, et al., Electron. Commun. Jpn. 2, Electron. vol. 81, pp. 18-25, 1998.