Test data compression and test resource partitioning for system-on-a-chip using frequency-directed run-length (FDR) codes

IEEE Transactions on Computers

Volumn 52, Issue 8, 2003, Pages 1076-1088

  Chandra, Anshuman ^a   Chakrabarty, Krishnendu ^a  

^a Duke University   (United States)

Author keywords

Automatic test equipment (ATE); Decompression architecture; Embedded core testing; Precomputed test sets; System on a chip test; Test set encoding; Variable to variable length codes

Indexed keywords

AUTOMATIC TESTING; BUILT-IN SELF TEST; CODES (SYMBOLS); COMPUTER SIMULATION; DATA COMPRESSION; FAILURE ANALYSIS; INTEGRATED CIRCUIT LAYOUT; MICROPROCESSOR CHIPS; PROBABILITY;

AUTOMATIC TEST EQUIPMENT; DECOMPRESSION ARCHITECTURE; EMBEDDED CORE TESTING; FREQUENCY DIRECTED RUN-LENGTH CODES; PRECOMPUTED TEST SETS; SYSTEM-ON-A-CHIP; TEST DATA COMPRESSION; TEST RESOURCE PARTITIONING; TEST SET ENCODING; VARIABLE TO VARIABLE LENGTH CODES;

INTEGRATED CIRCUIT TESTING;

EID: 0042564666     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/TC.2003.1223641     Document Type: Article

References (27)

1. Y. Zorian, E.J. Marinissen, and S. Dey, "Testing Embedded-Core Based System Chips," Proc. Int'l Test Conf., pp. 130-143, 1998.
2. B.T. Murray and J.P. Hayes, "Testing ICs: Getting to the Core of the Problem," Computer, vol. 29, no. 11, pp. 32-38, Nov. 1996.
3. V. Iyengar, K. Chakrabarty, and B.T. Murray, "Deterministic Built-In Self Testing of Sequential Circuits Using Precomputed Test Sets," J. Electronic Testing: Theory and Applications (JETTA), vol. 15, pp. 97-114, Aug./Oct. 1999.
4. A. Jas, J. Ghosh-Dastidar, and N.A. Touba, "Scan Vector Compression/Decompression Using Statistical Coding," Proc. IEEE VLSI Test Symp., pp. 114-120, 1999.
5. A. Jas and N.A. Touba, "Test Vector Decompression via Cyclical Scan Chains and Its Application to Testing Core-Based Design," Proc. Int'l Test Conf., pp. 458-464, 1998.
6. A. Chandra and K. Chakrabarty, "Test Data Compression for System-on-a-Chip Using Golomb Codes," Proc. IEEE VLSI Test Symp., pp. 113-120, 2000.
7. A. Chandra and K. Chakrabarty, "System-On-a-Chip Test Data Compression and Decompression Architectures Based on Golomb Codes," IEEE Trans. Computer-Aided Design, vol. 20, no. 3, pp. 355-368, Mar. 2001.
8. D. Salomon, Data Compression, second ed. Springer-Verlag, 2000.
9. H. Ichihara, K. Kinoshita, I. Pomeranz, and S.M. Reddy, "Test Transformation to Improve Compaction by Statistical Encoding," Proc. Int'l Conf. VLSI Design, pp. 294-299, 2000.
10. A. Chandra and K. Chakrabarty, "Efficient Test Data Compression and Decompression for System-On-a-Chip Using Internal Scan Chains and Golomb Coding," Proc. Design, Automation, and Test in Europe (DATE) Conf., pp. 145-149, 2001.
11. A. Chandra and K. Chakrabarty, "Test Resource Partitioning and Reduced Pin-Count Testing Based on Test Data Compression," Proc. Design, Automation and Test in Europe (DATE) Conf., pp. 598-603, 2002.
12. A. Chandra and K. Chakrabarty, "Combining Low-Power Scan Testing and Test Data Compression for System-On-a-Chip," Proc. IEEE/ACM Design Automation Conf. (DAC), pp. 166-169, June 2001.
13. J. Saxena, K. Butler, and L. Whetsel, "An Analysis of Power Reduction Techniques in Scan Testing," Proc. Int'l Test Conf., pp. 670-677, 2001.
14. M. Berkelaar, lpsolve. version 3.0. Eindhoven Univ. of Technology, Design Automation Section, Eindhoven, The Netherland, ftp://ftp.ics.ele.nl/pub/lp_solve, 2000.
15. S.C. Ma, P. Franco, and E.J. McCluskey, "An Experimental Chip to Evaluate Test Techniques Experimental Results," Proc. Int'l Test Conf., pp. 663-672, 1995.
16. S.M. Reddy, I. Pomeranz, and S. Kajihara, "On the Effects of Test Compaction on Defect Coverage," Proc. IEEE VLSI Test Symp., pp. 430-435, 1996.
17. I. Pomeranz and S.M. Reddy, "Stuck-At Tuple-Detection: A Fault Model Based on Stuck-At Faults for Improved Defect Coverage," Proc. IEEE VLSI Test Symp., pp. 289-294, 1998.
18. S. Hellebrand, H.-G. Liang, and H.-J. Wunderlich, "A Mixed-Mode BIST Scheme Based on Reseeding of Folding Counters," Proc. Int'l Test Conf., pp. 778-784, 2000.
19. H.-J. Wunderlich and G. Kiefer, "Bit-Flipping BIST," Proc. Int'l Conf. Computer-Aided Design, pp. 337-343, 1996.
20. N.A. Touba and E.J. McCluskey, "Altering a Pseudo-Random Bit Sequence for Scan Based BIST," Proc. Int'l Test Conf., pp. 167-175, 1996.
21. I. Hamzaoglu and J.H. Patel, "Reducing Test Application Time for Full Scan Embedded Cores," Proc. Int'l Symp. Fault-Tolerant Computing, pp. 260-267, 1999.
22. J. Teuhola, "A Compression Method for Clustered Bit-Vectors," Information Processing Letters, vol. 7, pp. 308-311, Oct. 1978.
23. I. Hamzaoglu, and J.H. Patel, "Test Set Compaction Algorithms for Combinational Circuits," Proc. Int'l Conf. Computer-Aided Design, pp. 283-289, 1998.
24. H. Kobayashi and L.R. Bahl, "Image Data Compression by Predictive Coding, Part I: Prediction Algorithm," IBM J. Research and Development, vol. 18, p. 164, 1974.
25. J.A. Storer, Data Compression: Methods and Theory. New York: Computer Science Press, 1988.
26. Design Compiler Reference Manual. Synopsys Inc., 1992.
27. Univ. of Illinois IGATE website, www.crhc.uiuc.edu/IGATE, 2000.