Testing ICs: Getting to the core of the problem

Computer

Volumn 29, Issue 11, 1996, Pages 32-38

  Murray, Brian T ^a,b,c,d,e   Hayes, John P ^{b,e,f,g,h,i,j}  

^a GENERAL MOTORS CORPORATION   (United States)

^b UNIVERSITY OF MICHIGAN   (United States)

^c ALBION COLLEGE   (United States)

^d DUKE UNIVERSITY   (United States)

^e IEEE

^f UNIVERSITY OF SOUTHERN CALIFORNIA   (United States)

^g UNIVERSITY OF MICHIGAN   (United States)

^h Michigan's Adv Comp Arch Lab ^*

ⁱ UNIVERSITY COLLEGE DUBLIN   (Ireland)

^j UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

more..

Author keywords

[No Author keywords available]

Indexed keywords

COSTS; INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUIT MANUFACTURE; ONLINE SYSTEMS; TECHNOLOGY;

BUILT IN SELF TEST; CORES; DESIGN TESTING; DESIGN TO REST TECHNIQUES; FAULT MODELS; MANUFACTURING TESTING; TEST GENERATION METHODS;

INTEGRATED CIRCUIT TESTING;

EID: 0030291568     PISSN: 00189162     EISSN: None     Source Type: Trade Journal    
DOI: 10.1109/2.544235     Document Type: Review

References (12)

1. K.M. Thompson, "Intel and the Myths of Test," Proc. Int'l Test Conf., IEEE CS Press, Los Alamitos, Calif., 1995 (keynote address).
2. M. Abramovici, M.A. Breuer, and A.D. Friedman, Digital Systems Testing and Testable Design, Computer Science Press, New York, 1990.
3. M.H. Schulz, E. Trischler, and T.M. Sarfert, "Socrates: A Highly Efficient Automatic Test Pattern Generation System," IEEE Trans. Computer-Aided Design, Jan. 1988, pp. 126-137.
4. I. Pomeranz, L.N. Reddy, and S.M. Reddy, "CompacTest: A Method to Generate Compact Test Sets for Combinational Circuits," Proc. Int'l Test Conf., IEEE CS Press, Los Alamitos, Calif., 1991, pp. 194-203.
5. D. Bhattacharya, B.T. Murray, and J.P. Hayes, "High-Level Test Generation for VLSI," Computer, Apr. 1989, pp. 16-24.
6. F.J. Ferguson and J.P. Shen, "A CMOS Fault Extractor for Inductive Fault Analysis," IEEE Trans. Computer-Aided Design, Vol. 7, pp. 1,181-1,194, November, 1988.
7. R.T. Maniwa, "Design for Test Tools," Integrated System Design, Sept. 1996, pp. 60-74.
8. K. Chakrabarty, B.T. Murray, and J.P. Hayes, "Optimal Space Compaction of Test Responses," Proc. Int'l Test Conf., International Test Conference, Altoona, Penn., 1995, pp. 834-843.
9. G. Persky, D.N. Deutsch, and D.G. Schweikert, "LTX - A Minicomputer-Based System for Automated LSI Layout," J. Design Automation and Fault-Tolerant Computing, May 1977, pp. 217-255.
10. B.T. Murray and J.P. Hayes, "Hierarchical Test Generation Using Precomputed Tests for Modules," IEEE Trans. Computer-Aided Design, Sept. 1990, pp. 594-603.
11. J. Lee and J.H. Patel. "Architectural Level Test Generation for Microprocessors," IEEE Trans. Computer-Aided Design, Oct. 1994, pp. 1,288-1,300.
12. F. Beenker et al., "A Testability Strategy for Silicon Compilers," Proc. Int'l Test Conf., IEEE CS Press, Los Alamitos, Calif., 1989, pp. 660-668.