메뉴 건너뛰기




Volumn , Issue , 2002, Pages 598-603

Test resource partitioning and reduced pin-count testing based on test data compression

Author keywords

[No Author keywords available]

Indexed keywords

BOUNDARY SCAN; DEFECT COVERAGE; EMBEDDED CORES; RUN-LENGTH CODE; SYSTEM-ON-A-CHIP; TEST DATA COMPRESSION; TEST RESOURCE PARTITIONING; TEST-DATA VOLUME;

EID: 0011840592     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2002.998362     Document Type: Conference Paper
Times cited : (15)

References (14)
  • 1
    • 0032636437 scopus 로고    scopus 로고
    • Testing the monster chip
    • July
    • Y. Zorian, "Testing the monster chip." IEEE Spectrum, vol. 36, issue 7, pp. 54-70, July 1999.
    • (1999) IEEE Spectrum , vol.36 , Issue.7 , pp. 54-70
    • Zorian, Y.1
  • 2
    • 0024917438 scopus 로고
    • Low cost testing of high density logic components
    • R. W. Basset et al., "Low cost testing of high density logic components", Proc. Int. Test Conf., pp. 550-557, 1989.
    • (1989) Proc. Int. Test Conf. , pp. 550-557
    • Basset, R.W.1
  • 4
    • 0035445025 scopus 로고    scopus 로고
    • Test resource partitioning for SOCs
    • September-October
    • A. Chandra and K. Chakrabarty, "Test resource partitioning for SOCs", IEEE Design & Test of Computers, vol. 18, pp. 80-91, September-October 2001.
    • (2001) IEEE Design & Test of Computers , vol.18 , pp. 80-91
    • Chandra, A.1    Chakrabarty, K.2
  • 5
    • 0032318126 scopus 로고    scopus 로고
    • Test vector decompression via cyclical scan chains and its application to testing corebased design
    • A. Jas and N. A. Touba, "Test vector decompression via cyclical scan chains and its application to testing corebased design", Proc. Int. Test Conf., pp. 458-464, 1998.
    • (1998) Proc. Int. Test Conf. , pp. 458-464
    • Jas, A.1    Touba, N.A.2
  • 6
    • 0035271735 scopus 로고    scopus 로고
    • System-on-a-chip test data compression and decompression architectures based on Golomb codes
    • March
    • A. Chandra and K. Chakrabarty, "System-on-a-chip test data compression and decompression architectures based on Golomb codes", IEEE Trans. CAD, vol. 20, pp. 355- 368, March 2001.
    • (2001) IEEE Trans. CAD , vol.20 , pp. 355-368
    • Chandra, A.1    Chakrabarty, K.2
  • 7
    • 84893648051 scopus 로고    scopus 로고
    • Efficient test data compression and decompression for system-on-a-chip using internal scan chains and Golomb coding
    • A. Chandra and K. Chakrabarty, "Efficient test data compression and decompression for system-on-a-chip using internal scan chains and Golomb coding", Proc. DATE Conf., pp. 145-149, 2001.
    • (2001) Proc. DATE Conf. , pp. 145-149
    • Chandra, A.1    Chakrabarty, K.2
  • 8
    • 0034994812 scopus 로고    scopus 로고
    • Frequency-directed runlength (FDR) codes with application to system-on-a-chip test data compression
    • A. Chandra and K. Chakrabarty, "Frequency-directed runlength (FDR) codes with application to system-on-a-chip test data compression", Proc. VLSI Test Symp., pp. 42-47, 2001.
    • (2001) Proc. VLSI Test Symp. , pp. 42-47
    • Chandra, A.1    Chakrabarty, K.2
  • 9
    • 0029510949 scopus 로고
    • An experimental chip to evaluate test techniques experimental results
    • S. C. Ma, P. Franco and E. J. McCluskey, "An experimental chip to evaluate test techniques experimental results", Proc. Int. Test Conf., pp. 663-672, 1995.
    • (1995) Proc. Int. Test Conf. , pp. 663-672
    • Ma, S.C.1    Franco, P.2    McCluskey, E.J.3
  • 10
    • 0029709722 scopus 로고    scopus 로고
    • On the effects of test compaction on defect coverage
    • S. M. Reddy, I. Pomeranz and S. Kajihara, "On the effects of test compaction on defect coverage", Proc. VLSI Test Symp., pp. 430-435, 1996.
    • (1996) Proc. VLSI Test Symp. , pp. 430-435
    • Reddy, S.M.1    Pomeranz, I.2    Kajihara, S.3
  • 11
    • 0032313243 scopus 로고    scopus 로고
    • Stuck-at tuple-detection: A fault model based on stuck-at faults for improved defect coverage
    • I. Pomeranz and S. M. Reddy, "Stuck-at tuple-detection: A fault model based on stuck-at faults for improved defect coverage", Proc. VLSI Test Symp., pp. 289-294, 1998.
    • (1998) Proc. VLSI Test Symp. , pp. 289-294
    • Pomeranz, I.1    Reddy, S.M.2
  • 13
    • 0032320384 scopus 로고    scopus 로고
    • Test set compaction algorithms for combinational circuits
    • I. Hamzaoglu and J. H. Patel, "Test set compaction algorithms for combinational circuits", Proc. Int. Conf. CAD, pp. 283-289, 1998.
    • (1998) Proc. Int. Conf. CAD , pp. 283-289
    • Hamzaoglu, I.1    Patel, J.H.2
  • 14
    • 0026618718 scopus 로고
    • An efficient forward fault simulation algorithm based on the parallel pattern single fault propagation
    • H. K. Lee and D. S. Ha. "An efficient forward fault simulation algorithm based on the parallel pattern single fault propagation" Proc. Int. Test Conf., pp. 946-955, 1991.
    • (1991) Proc. Int. Test Conf. , pp. 946-955
    • Lee, H.K.1    Ha, D.S.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.