Design of synchronous and asynchronous variable-latency pipelined multipliers

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 9, Issue 2, 2001, Pages 365-376

  Olivieri, M ^a  

^a SAPIENZA UNIVERSITY OF ROME   (Italy)

Author keywords

Arithmetic units; Asynchronous systems; Multipliers; VLSI design

Indexed keywords

ADDERS; ALGORITHMS; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; DIGITAL ARITHMETIC; EVALUATION; INTEGRATED CIRCUIT LAYOUT; LOGIC DESIGN; PERFORMANCE; VLSI CIRCUITS;

SECOND-ORDER BOOTH ALGORITHM; SOFTWARE PACKAGE SPEC95; VARIABLE-LATENCY PIPELINED MULTIPLIERS;

MULTIPLYING CIRCUITS;

EID: 0035300996     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/92.924058     Document Type: Article

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