An evaluation of asynchronous addition

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 4, Issue 1, 1996, Pages 137-140

  Kinniment, D J ^a  

^a NEWCASTLE UNIVERSITY   (United Kingdom)

Author keywords

Adders; Asynchronous binary addition; Asynchronous systems; CPU design; High performance systems; Micropipelines

Indexed keywords

COMPUTER HARDWARE; DIGITAL ARITHMETIC; LOGIC GATES; PIPELINE PROCESSING SYSTEMS; SYSTEMS ANALYSIS; TIMING CIRCUITS; TRANSISTORS;

ASYNCHRONOUS ADDITION; ASYNCHRONOUS SYSTEMS; CENTRAL PROCESSING UNIT DESIGN; HIGH PERFORMANCE SYSTEMS; MICROPIPELINES;

ADDERS;

EID: 0030110561     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/92.486088     Document Type: Review

References (12)

1. I. E. Sutherland, "Micropipelines," Commun. ACM, vol. 32, no. 6, pp. 720-738, June 1989.
2. S. B. Furber, P. Day, J. D. Garside, N. C. Paver, and J. V. Woods, "AMULET1: A micropipelined ARM," in IEEE CompCon 94, San Francisco, CA, Mar. 1994.
3. A. W. Burks, H. H. Goldstine, and J. von Neumann, "Preliminary discussion of the logical design of and electronic computing instrument," Inst. Advanced Study, Princeton, NJ, June 28, 1947.
4. B. Gilchrist, J. H. Pomerene, and S. Y. Wong, "Fast carry logic for digital computers," IRE Trans. Electron. Comput. vol. EC-4, pp. 133-136, Dec. 1955.
5. C. Mead and L. Conway, Introduction to VLSI Systems. Reading, MA: Addison-Wesley, 1980, ISBN 0-210-04358-0, pp. 247-252.
6. J. D. Garside, "A CMOS VLSI implementation of an asynchronous ALU," in Proc. IFIP Conf. Asynchronous Design Methodologies, Manchester, UK, 1993.
7. J. Sklansky, "An evaluation of several two-summand, binary adders," IRE Trans. Electron. Comput., vol. EC-9, pp. 213-226, 1960.
8. _, "Conditional-sum addition logic," IRE Trans. Electron. Comput., vol. EC-9, pp. 226-231, 1960.
9. O. J. Bedrij, "Carry select adder," IRE Trans. Electron. Comput., vol. EC-11, pp. 340-346, 1962.
10. G. W. Reitwiesner, "The determination of carry propagation length for binary addition," IRE Trans. Electron. Comput., vol. EC-9, pp. 35-38, 1960.
11. B. E. Briley, "Some new results on average worst-case cany," IEEE Trans. Comput., vol. C-22, pp. 459-463, 1973.
12. M. A. Franklin and T. Pan, "Performance comparison of asynchronous adders," in Proc. Symp. Advanced Res. Asynchronous Ciruits and Syst., Salt Lake City, UT, Nov. 1994, pp. 117-125.