VLSI design of an asynchronous multiplier with data dependant processing times

Proceedings of the Australian Microelectronics Conference

Volumn , Issue , 1997, Pages 282-287

  Kearney, D ^a   Bergmann, N W ^a  

^a UNIVERSITY OF SOUTH AUSTRALIA   (Australia)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; DELAY CIRCUITS; LOGIC DESIGN; MULTIPLYING CIRCUITS; VLSI CIRCUITS;

ASYNCHRONOUS LOGIC; ASYNCHRONOUS MULTIPLIER; HANDSHAKING CONTROL CIRCUITS; MICROPIPELINES;

INTEGRATED CIRCUIT LAYOUT;

EID: 0031368848     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (9)