AMULET2e: An asynchronous embedded controller

Proceedings of the IEEE

Volumn 87, Issue 2, 1999, Pages 243-256

  Furber, Stephen B ^a   Garside, James D ^a   Riocreux, Peter ^b   Temple, Steven ^c   Day, Paul ^b   Liu, Jianwei ^b   Paver, Nigel C ^a  

^a UNIVERSITY OF MANCHESTER   (United Kingdom)

^b 2n Design Ltd   (United Kingdom)

^c Cogency Technology Inc ^*  (United Kingdom)

Author keywords

Asynchronous logic circuits; CMOS digital integrated circuits; Digital systems; Electromagnetic compatibility; Integrated circuit design; Microprocessors

Indexed keywords

BUFFER STORAGE; CMOS INTEGRATED CIRCUITS; ELECTROMAGNETIC COMPATIBILITY; ELECTROMAGNETIC WAVE INTERFERENCE; LOGIC DESIGN; MICROCONTROLLERS; PIPELINE PROCESSING SYSTEMS; PROGRAMMABLE LOGIC CONTROLLERS;

FLEXIBLE MEMORY INTERFACES;

ASYNCHRONOUS SEQUENTIAL LOGIC;

EID: 0033079573     PISSN: 00189219     EISSN: None     Source Type: Journal    
DOI: 10.1109/5.740018     Document Type: Article

References (30)

1. A. J. Martin, S. M. Burns, T. K. Lee, D. Borkovic, and P. J. Hazewindus, "The design of an asynchronous microprocessor," in Advanced Research in VLSI: Proceedings of the Decennial Caltech Conference on VLSI, C. Seitz, Ed. Cambridge, MA: MIT Press, 1989, pp. 351-373.
2. A. J. Martin, A. Lines, R. Manohar, M. Nystrom, P. Penzes, R. Southworth, U. Cummings, and T. K. Lee, "The design of an asynchronous MIPS R3000 microprocessor," in P roc. 17th Conf. Advanced Research in VLSI, 1997, pp. 164-181.
3. T. Nanya, Y. Ueno, H. Kagotani, M. Kuwako, and A. Takamjura, "TITAC: Design of a quasidelay-insensitive microprocessor," IEEE Design Test Comput., vol. 11, pp. 50-63, Feb. 1994.
4. A. Takamura, M. Kuwako, M. Imai, T. Fujii, M. Ozawa, I. Fukasaku, Y, Ueno, and T. Nanya, "TITAC-2: An asynchronous 32-bit microprocessor based on scalable-delay insensitive model," in Proc. ICCD'97, pp. 288-294.
5. H. van Gageldonk, K. van Berkel, and A. Peeters, "An asynchronous low-power 80C51 microcontroller," in Proc. 4th Int. Symp. Advanced Research in Asynchronous Circuits and Systems-(Async'98), pp. 96-107.
6. R. F. Sproull, I. E. Sutherland, and C. E. Molnar, "Counterflow pipeline processor architecture," IEEE Design Test Comput., vol. 11, pp. 48-59, Mar. 1994.
7. W. F. Richardson and E. Brunvand, "Architectural considerations for a self-timed decoupled processor," Inst. Elect. Eng. Proc. Computers and Digital Techniques, vol. 143, no. 5, pp. 251-257, Sept. 1996.
8. S. Moore, P. Robinson, and S. Wilcox, "Rotary pipeline processors," Imt. Elect. Eng. Proc. Computers and Digital Techniques, Sept. 1996, vol. 143, no. 5, pp. 259-265.
9. C. J. Eiston, D. B. Christianson, P. A. Findlay, and G. B. Steven, "Hades-Toward the design of an asynchronous superscalar processor," in Proc. 2nd Working Conf. Asynchronous Design Methodologies, 1995, pp. 200-209.
10. K. Christensen, P. Jensen, P. Korger, and J. Sparso, "The design of an asynchronous TinyRISC TR4101 microprocessor core," in Proc. 4th Int. Symp. Advanced Research in Asynchronous Circuits and Systems (Async'98), pp. 108-119.
11. M. Renaudin, P. Vivet, and F. Robin, "ASPRO-216: A standardcell Q.D.I. 16-bit RISC asynchronous microprocessor," in Proc. 4th Int. Symp. Advanced Research in Asynchronous Circuits and Systems (Async'98), pp. 22-31.
12. N. C. Paver, "The design and implementation of an asynchronous microprocessor," Ph.D dissertation, Dep. Comput. Sei., Univ. Manchester, U.K., June 1994.
13. J. V. Woods, P. Day, S. B. Furber, J. D. Garside, N. C. Paver, and S. Temple, "AMULET1: An asynchronous ARM microprocessor," IEEE Trans. Comput., vol. 46, pp. 385-398, Apr. 1997.
14. S. B. Furber, ARM System Architecture. Reading, MA: Addison-Wesley, 1996.
15. I. E. Sutherland, "Micropipelines," Commun. ACM, vol. 32, no. 6, pp. 720-738, Jan. 1989.
16. S. B. Furber, J. D. Garside, S. Temple, J. Liu, P. Day, and N. C. Paver, "AMULET2e: An asynchronous embedded controller," in Proc. 3rd Int. Symp. Advanced Research in Asynchronous Circuits and Systems (Async'97). pp. 290-299.
17. S. B. Furber, P. Day, J. D. Garside, N. C. Paver, and J. V. Woods, "A micropipelined ARM," in Proc. IFIP TC 10AVG 10.5 Int. Conf. Very Large Scale Integration (VLSI'93), T. Yanagawa and P. A. Ivey, Eds., North Holland, 1993, pp. 211-220.
18. _, "AMULET1: A micropipelined ARM," in Proc. CompCon'94, pp. 476-485.
19. _, "The design and evaluation of an asynchronous microprocessor," in Proc. ICCD'94, pp. 217-220.
20. S. B. Furber, "Computing without clocks: Micropipelining the ARM processor," in Asynchronous Digital Circuit Design, G. Birtwistle and A. Davis, Eds. New York: Springer, 1995, pp. 211-262.
21. N. C. Paver, P. Day, S. B. Furber, J. D. Garside, and J. V. Woods, "Register locking in an asynchronous microprocessor," in Proc. ICCD'92, pp. 351-355.
22. J. D. Garside, "A CMOS VLSI implementation of an asynchronous ALU," in Asynchronous Design Methodologies, S. B. Furber and M. D. Edwards, Eds. Amsterdam, The Netherlands: North Holland, 1993, pp. 181-192.
23. S. B. Furber and P. Day, "Four-phase micropipeline latch control circuits," IEEE Trans. VLSI Syst., vol. 4, pp. 247-253, June 1996.
24. D. Morris and R. N. Ibbett, The MU5 Computer System. New York: Macmillan, 1979.
25. J. D. Garside, S. Temple, and R. Mehra, "The AMULET2e cache system," in Proc. 2nd Int. Symp. Advanced Research in Asynchronous Circuits and Systems (Async'96), pp. 208-217.
26. R. Mehra and J. D. Garside, "A cache line fill circuit for a micropipelined asynchronous microprocessor," TCCA Newsletter, IEEE Computer Society, Oct. 1995.
27. AMULET2e data sheet, Dept. of Computer Science, Univ. Manchester, U.K. [Online]. Available WWW: http://ww\v.cs.man.ac.uk/amulet/AMULET2e_uP.html.
28. M. Kishinevsky, A. Kondratyev, and A. Taubin, Concurrent Hardware. New York: Wiley, 1994.
29. P. Endecott and S. B. Furber, "Modeling and simulation of asynchronous systems using the LARD hardware description language," in Proc. ESM '98: (12th Europ. Simulation Mulli-conf.), pp. 39-43.
30. J. Liu, "The design of an asynchronous multiplier," M.Sc. thesis, Dep. Comput. Sei., Univ. Manchester, U.K., Oct. 1995.