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Volumn 145, Issue 1, 1998, Pages 1-7

Design and analysis of asynchronous adders

Author keywords

Asynchronous adders; Asynchronous pipelines; Carry propagation chains; Data dependent computation delay

Indexed keywords

ASYNCHRONOUS MACHINERY; DATA TRANSFER; DELAY CIRCUITS; DESIGN; GATEWAYS (COMPUTER NETWORKS); PERFORMANCE;

EID: 0031707557     PISSN: 13502387     EISSN: None     Source Type: Journal    
DOI: 10.1049/ip-cdt:19981770     Document Type: Article
Times cited : (22)

References (11)
  • 8
    • 33745979106 scopus 로고    scopus 로고
    • Proceedings of the IFIP conference on Asynchronous design methodologies, Manchester, UK, 1993
    • GARSIDE, J.D.: 'A CMOS VLSI implementation of an asynchronous ALU' Proceedings of the IFIP conference on Asynchronous design methodologies, Manchester, UK, 1993
    • 'A CMOS VLSI Implementation of An Asynchronous ALU'
    • Garside, J.D.1
  • 9
    • 0028743583 scopus 로고    scopus 로고
    • Proceedings IEEE international symposium on Advanced research in asynchronous circuits and systems, ASYNC-94, Salt Lake City, Utah, 1994, pp. 117-125
    • FRANKLIN, M.A., and PAN, T.: ' and, 'Performance comparison of asynchronous adders' Proceedings IEEE international symposium on Advanced research in asynchronous circuits and systems, ASYNC-94, Salt Lake City, Utah, 1994, pp. 117-125
    • ' And, 'Performance Comparison of Asynchronous Adders'
    • Franklin, M.A.1    Pan, T.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.