Early-completion-detecting ALU for a 1 GHz 64 b datapath

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 40, Issue , 1997, Pages 418-419

  Kondo, Yoshihiasa ^a   Ikumi, Nobuyuki ^a   Ueno, Kiyoji ^a   Mori, Junji ^a   Hirano, Masashi ^a  

^a TOSHIBA CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ADDERS; COMPUTER SIMULATION; DETECTOR CIRCUITS; DIGITAL ARITHMETIC; LOGIC GATES; MICROPROCESSOR CHIPS; PIPELINE PROCESSING SYSTEMS; REDUCED INSTRUCTION SET COMPUTING; TRANSISTORS;

ARITHMETIC LOGIC UNIT (ALU); SOFTWARE PACKAGE SPICE;

LOGIC CIRCUITS;

EID: 0031073169     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (0)