180 Mhz 16 bit multiplier using asynchronous logic design techniques

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 1994, Pages 215-218

  Burford, Richard G ^a   Fan, Xiangcha ^a   Bergmann, Neil W ^a  

^a FLINDERS UNIVERSITY   (Australia)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; DIGITAL INTEGRATED CIRCUITS; DIGITAL SIGNAL PROCESSING; FREQUENCY MULTIPLYING CIRCUITS; LOGIC CIRCUITS; PERFORMANCE; TRANSISTORS;

ASYNCHRONOUS DESIGN TECHNIQUE; CMOS DIGITAL LOGIC DESIGN TECHNIQUE; DEGRADATION FACTORS; DIFFERENTIAL CASCODE VOLTAGE SWITCH LOGIC; LATCH DESIGN;

LOGIC DESIGN;

EID: 0028098404     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (11)