TITAC-2: An asynchronous 32-bit microprocessor based on scalable-delay-insensitive model

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Volumn , Issue , 1997, Pages 288-294

  Takamura, Akihiro ^a   Kuwako, Masashi ^a   Imai, Masashi ^a   Fujii, Taro ^a   Ozawa, Motokazu ^a   Fukasaku, Izumi ^a   Ueno, Yoichiro ^a   Nanya, Takashi ^a  

^a TOKYO INSTITUTE OF TECHNOLOGY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

INTEGRATED CIRCUIT LAYOUT; VLSI CIRCUITS;

SCALABLE DELAY INSENSITIVE (SDI) MODEL;

MICROPROCESSOR CHIPS;

EID: 0031336623     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (15)