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Volumn 2, Issue , 1995, Pages 761-764
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Design and implementation of asynchronous parallel multiply-accumulate arithmetic architectures
a
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Author keywords
[No Author keywords available]
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Indexed keywords
ADDERS;
ALGORITHMS;
APPLICATION SPECIFIC INTEGRATED CIRCUITS;
DIGITAL ARITHMETIC;
DIGITAL COMPUTERS;
DIGITAL SIGNAL PROCESSING;
GATES (TRANSISTOR);
PARALLEL PROCESSING SYSTEMS;
PERFORMANCE;
SIGNAL ENCODING;
ASYNCHRONOUS PARALLEL MULTIPLY ACCUMULATE ARITHMETIC ARCHITECTURE;
BAUGH-WOOLEY ARRAY MULTIPLICATION ALGORITHMS;
GATE LEVEL PARAMETERIZATION;
MODIFIED BOOTH MULTIPLICATION ALGORITHMS;
PARTIAL PRODUCT SUMS;
SIGNED BINARY REPRESENTATION;
WORDLENGTHS;
COMPUTER ARCHITECTURE;
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EID: 0029461769
PISSN: None
EISSN: None
Source Type: Conference Proceeding
DOI: None Document Type: Conference Paper |
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Times cited : (3)
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References (12)
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