Design and characterisation of a CMOS VLSI self-timed multiplier architecture based on a bit-level pipelined-array structure

IEE Proceedings: Circuits, Devices and Systems

Volumn 145, Issue 4, 1998, Pages 247-253

  Acosta, A J ^a   Jimenez R ^a   Barriga, A ^a   Bellido, M J ^a   Valencia, M ^a   Huertas, J L ^a  

^a INSTITUTO DE MICROELECTRÓNICA DE SEVILLA   (Spain)

Author keywords

Multipliers; Pipelined arrays; Self timed circuits; Vlsi electronics

Indexed keywords

CMOS INTEGRATED CIRCUITS; DESIGN; MULTIPLYING CIRCUITS; PERFORMANCE;

PIPELINED ARRAYS;

VLSI CIRCUITS;

EID: 0032139967     PISSN: 13502409     EISSN: None     Source Type: Journal    
DOI: 10.1049/ip-cds:19982125     Document Type: Article

References (7)

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