2.7 ns 0.25 μm CMOS 54×54 b multiplier

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 1998, Pages 296-297,-449

  Hagihara, Y ^a   Inui, S ^a   Yoshikawa, A ^a   Nakazato, S ^a   Iriki, S ^a   Ikeda, R ^a   Shibue, Y ^a   Inaba, T ^a   Kagamihara, M ^a   Yamashina, M ^a  

^a NEC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ADDERS; CMOS INTEGRATED CIRCUITS; DIGITAL ARITHMETIC; LOGIC GATES; PIPELINE PROCESSING SYSTEMS; RESPONSE TIME (COMPUTER SYSTEMS);

BOOTH RECORDERS; DUAL RAIL DOMINO LOGIC GATES; FLOATING PROCESSING UNITS (FPU); PARTIAL PRODUCT GENERATORS; PASS TRANSISTOR LOGIC GATES;

MICROPROCESSOR CHIPS;

EID: 0031700808     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)