DDMP's: Self-timed super-pipelined data-driven multimedia processors

Proceedings of the IEEE

Volumn 87, Issue 2, 1999, Pages 282-296

  Terada, Hiroaki ^a   Miyata, Souichi ^b   Iwata, Makoto ^c  

^a KOCHI UNIVERSITY OF TECHNOLOGY   (Japan)

^b SHARP CORPORATION   (Japan)

^c Waseda University   (Japan)

Author keywords

Asynchronous pipeline; BOPS; Consumer appliances; Data driven, dataflow; Diagrammatic program language; Digital signal processing; Low power consumption; Self timed; VLSI processors

Indexed keywords

COMPUTER PROGRAMMING LANGUAGES; DIGITAL SIGNAL PROCESSING; MICROPROCESSOR CHIPS; MULTIMEDIA SYSTEMS; PIPELINE PROCESSING SYSTEMS; VLSI CIRCUITS;

DATA DRIVEN MULTIMEDIA PROCESSORS (DDMP);

ASYNCHRONOUS SEQUENTIAL LOGIC;

EID: 0033080039     PISSN: 00189219     EISSN: None     Source Type: Journal    
DOI: 10.1109/5.740021     Document Type: Article

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