On the adaptation of Viterbi algorithm for diagnosis of multiple bridging faults

IEEE Transactions on Computers

Volumn 49, Issue 6, 2000, Pages 575-587

  Thibeault, C ^a,b  

^a IEEE   (Canada)

^b ÉCOLE DE TECHNOLOGIE SUPÉRIEURE   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

MULTIPLE BRIDGING FAULTS; VITERBI ALGORITHMS;

ALGORITHMS; COMPUTER SIMULATION; ELECTRIC FAULT CURRENTS; ERROR CORRECTION; MAXIMUM LIKELIHOOD ESTIMATION;

INTEGRATED CIRCUIT TESTING;

EID: 0034204956     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/12.862217     Document Type: Article

References (41)

1. IEEE Test Technology Technical Committee, "A D&T Roundtable: Deep-Submicron Test," IEEE Design and Test of Computers, vol. 13, no. 3, pp. 102-108, Fall 1996.
2. E. Isern and J. Figueras, "IDDQ Test and Diagnosis of CMOS Circuits," IEEE Design and Test of Computers, vol. 12, no. 4, pp. 60-67, Winter 1995.
3. R.C. Aitken, "Diagnosis of Leakage Faults with IDDQ," J. Electronic Testing: Theory and Applications, vol. 3, no. 4, pp. 367-376, Dec. 1992.
4. R.C. Aitken, "Faults Location with Current Monitoring," Proc. Int'l Test Conf., pp. 623-623, 1991.
5. J.M. Soden and R.E. Anderson, "IC Failure Analysis: Techniques and Tool for Quality and Reliability Improvement," Proc. IEEE, vol. 81, no. 5, pp. 703-715, May 1994.
6. T. Lee et al., "Circuit-Level Dictionaries of CMOS Bridging Faults," Proc. IEEE VLSI Test Symp., pp. 386-391, 1994.
7. J.A. Waicukauski and E. Lindbloom, "Failure Diagnosis of Structured VLSI," IEEE Design and Test of Computers, vol. 6, no. 4, pp. 49-60, Fall 1989.
8. S. Chakravarty and M. Liu, "Algorithms for IDDQ Measurement Based Diagnosis of Bridging Faults," J. Electronic Testing: Theory and Applications, vol. 3, no. 4, pp. 377-386, Dec. 1992.
9. J.M. Soden, C.F. Hawkins, and A.C. Miller, "Identifying Defects in Deep-Submicron CMOS ICs," IEEE Spectrum, vol. 33, no. 9, pp. 66-71, Sept. 1996.
10. S.P. Athan, D.L. Landis, and S.A. Al-Arain, "A Novel Built-In Current Sensor for IDDQ Testing of Deep Submicron CMOS ICs," Proc. IEEE VLSI Test Symp, pp. 118-123, 1996.
11. J.G. Proakis, Digital Communications, third ed. New York: McGraw-Hill, 1983.
12. A.E. Gattiker and W. Maly, "Current Signatures," Proc. IEEE VLSI Test Symp., pp. 112-117, 1996.
13. F. Brglez and H. Fujiwara, "A Neutral Netlist of 10 Combinatorial Benchmark Circuits and a Target Translator in FORTRAN," Proc. Int'l Soc. Computer-Aided Surgery, pp. 695-698, 1985.
14. C. Thibeault, "A Novel Probabilistic Approach for IC Diagnosis Based on Differential Quiescent Current Signatures," Proc. IEEE VLSI Test Symp., pp. 80-85, 1997.
15. R. Rodriguez-Montanes, E.M.J.G. Bruls, and J. Figueras, "Bridging Defects Resistance Measurements in a CMOS Process," Proc. IEEE Int'l Test Conf., pp. 892-899, 1992.
16. A.H. Bowker and G.J. Lieberman, Engineering Statistics, second ed. Englewood Cliffs, N.J.: Prentice Hall, 1972.
17. S.M. Ross, Introduction to Probability Models, third ed. Orlando, Fla.: Academic Press, 1985.
18. A.E. Gattiker and W. Maly, "Current Signatures: Application," Proc. IEEE Int'l Test Conf., pp. 156-165, 1997.
19. P. Nigh, W. Needham, K. Butler, P. Maxwell, and R. Aitken, "An Experimental Study Comparing the Relative Effectiveness of Functional, Scan, Iddq, and Delay-Fault Testing," Proc. IEEE VLSI Test Symp., pp. 459-463, 1997.
20. C. Thibeault, "On the Current Behavior of Faulty and Fault-Free ICs and the Impact on Diagnosis," Proc. IEEE Int'l Symp. Defect and Fault Tolerance., pp. 202-210, 1998.
21. C. Thibeault, "On the Comparison of Delta Iddq and Iddq Testing," Proc. IEEE VLSI Test Symp., pp. 143-150, 1999.
22. IEEE Test Technology Technical Committee, "Sematech Experiment Roundtable," IEEE Design and Test of Computers, vol. 15, no. 1, p. 89, Jan.-Mar. 1998.
23. T. Williams, R. Dennard, R. Kapur, M. Mercer, and W. Maly, "Iddq Test: Sensitivity Analysis of Scaling," Proc. IEEE Int'l Test Conf., pp. 786-792, Oct. 1996.
24. C. Thibeault, "Increasing Current Testing Resolution," Proc. IEEE Int'l Symp. Defect and Fault Tolerance, pp. 126-134, 1998.
25. C. Thibeault and L. Boisvert, "Diagnosis Method Based on Δ Iddq Probabilistic Signatures: Experimental Results," Proc. IEEE Int'l Test Conf., pp. 1,019-1,026, 1998.
26. I. Koren and Z. Koren, "Defect Tolerance in VLSI Circuits: Techniques and Yield Analysis," Proc. IEEE, vol. 86, no. 9, pp. 1,819-1,838, Sept. 1998.
27. P. Nigh, D. Vallett, J. Wright, F. Motika, D. Forlenza, R. Kurtulik, and W. Chong, "Failure Analysis of Timing and Iddq-Only Failures from the SEMATECH Test Methods Experiment" Proc. IEEE Int'l Test Conf., pp. 43-52, 1998.
28. A. Kinra, A. Mehta, N. Smith, J. Mitchell, and F. Valente, "Diagnostic Techniques for the UltraSPARC™ Microprocessors," Proc. IEEE Int'l Test Conf., pp. 480-486, 1998.
29. J. Saxena et al., "On Applying Non-Classical Defect Models to Automated Diagnosis," Proc. IEEE Int'l Test Conf., pp. 748-757, 1998.
30. Y.C. Hsu and S.K. Gupta, "A New Path-Oriented Effect-Cause Methodology to Diagnose Delay Failures," Proc. IEEE Int'l Test Conf., pp. 758-767, 1998.
31. I. Pomeranz and S. Reddy, "A Diagnostic Test Generation Procedure for Synchronous Sequential Circuits Based on Test Elimination," Proc. IEEE Int'l Test Conf., pp. 1,074-1,083, 1998.
32. D. Lavo, T. Larrabee, B. Chess, and I. Hartanto, "Probabilistic Mixed-Model Fault Diagnosis," Proc. IEEE Int'l Test Conf., pp. 1,084-1,093, 1998.
33. V. Boppana and M. Fujita, "Modeling the Unknown! Towards Model-Independent Fault and Error Diagnosis," Proc. IEEE Int'l Test Conf., pp. 1,094-1,101, 1998.
34. J.M. Soden, R.E. Anderson, and C.L. Henderson, "IC Failure Analysis: Magic, Mystery, and Science," IEEE Design and Test of Computers, vol. 13, no. 3, pp. 59-69, July-Sept. 1998.
35. D. Staab and E.R. Hnatek, "Diagnosing IC Failures in a Fast Environment," IEEE Design and Test of Computers, vol. 13, no. 3, pp. 70-75, July-Sept. 1998.
36. D.P. Vallett, "IC Failure Analysis: The Importance of Test and Diagnostics," IEEE Design and Test of Computers, vol. 13, no. 3, pp. 76-82, July-Sept. 1998.
37. K.M. Bulter et al., "Automated Diagnosis in Testing and Failure Analysis," IEEE Design and Test of Computers, vol. 13, no. 3, pp. 83-89, July-Sept. 1998.
38. R.C. Aitken, "Modeling the Unmodelable: Algorithmic Fault Diagnosis," IEEE Design and Test of Computers, vol. 13, no. 3, pp. 98-103, July-Sept. 1998.
39. H. Takahashi, N. Yanagida, and Y. Takamatsu, "Enhancing Multiple Fault Diagnosis in Combinatorial Circuits Based on Sensitized Paths and EB Testing," Proc. IEEE Fourth Asian Test Conf., pp. 58-64, 1995.
40. P. Nigh, D. Forlenza, and F. Motika, "Application and Analysis of Iddq Diagnostic Software," Proc. IEEE Int'l Test Conf., pp. 319-327, 1997.
41. L. Boisvert, "Validation d'une méthode de diagnostic basée sur les signatures probabilistes de ΔIddq," master's thesis (in French), École de technologie supérieure, Montréal, Canada, 1998.