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Volumn 14, Issue 3, 1997, Pages 70-75

Diagnosing IC Failures in a Fast Environment

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED DESIGN; CONCURRENT ENGINEERING; COST EFFECTIVENESS; DATABASE SYSTEMS; FAILURE ANALYSIS; INTEGRATED CIRCUIT LAYOUT; PROBLEM SOLVING; RELIABILITY;

EID: 0031186307     PISSN: 07407475     EISSN: None     Source Type: Journal    
DOI: 10.1109/54.606000     Document Type: Article
Times cited : (2)

References (10)
  • 1
    • 0005944837 scopus 로고
    • A Comparison of Defect Models for Fault Location with IDDQ Measurement
    • Los Alamitos, Calif.
    • Aitken, R., “A Comparison of Defect Models for Fault Location with IDDQ Measurement,” Proc. Int'l Test Conf., IEEE Computer Society Press, Los Alamitos, Calif., 1992, pp. 778-787.
    • (1992) Proc. Int'l Test Conf., IEEE Computer Society Press , pp. 778-787
    • Aitken, R.1
  • 2
    • 0039971474 scopus 로고
    • A Study of IDDQSubset Selection Algorithms for Bridging Faults
    • Chakravarty, S., and P. Thadikaran, “A Study of IDDQSubset Selection Algorithms for Bridging Faults,” Proc. Int'l Test Conf., 1994, pp. 403-412.
    • (1994) Proc. Int'l Test Conf. , pp. 403-412
    • Chakravarty, S.1    Thadikaran, P.2
  • 3
    • 0027870143 scopus 로고
    • The Cost of Quality: Reducing ASIC Defects with IDDQ,AtSpeed Testing, and Increased Fault Coverage
    • Gayle, R., “The Cost of Quality: Reducing ASIC Defects with IDDQ,AtSpeed Testing, and Increased Fault Coverage,” Proc. Int'l Test Conf., 1993, pp. 285-292.
    • (1993) Proc. Int'l Test Conf. , pp. 285-292
    • Gayle, R.1
  • 4
    • 0000738845 scopus 로고
    • Defect Classes: An Overdue Paradigm for CMOS IC Testing
    • Hawkins, C.F., et al., “Defect Classes: An Overdue Paradigm for CMOS IC Testing,” Proc. Int'l Test Conf., 1994, pp. 413-425.
    • (1994) Proc. Int'l Test Conf. , pp. 413-425
    • Hawkins, C.F.1
  • 5
    • 0011798198 scopus 로고
    • Fault Location in Full-Scan Designs
    • ASM Int'l, Materials Park, Oh.
    • Kunda, R.P., “Fault Location in Full-Scan Designs,” Proc. 19th Int'l Symp. Testing and Failure Analysis, ASM Int'l, Materials Park, Oh., 1993, pp. 121-127.
    • (1993) Proc. 19th Int'l Symp. Testing and Failure Analysis , pp. 121-127
    • Kunda, R.P.1
  • 6
    • 0002650001 scopus 로고
    • The Effectiveness of IDDQ, Functional, and Scan Tests: How Many Fault Coverages Do We Need?
    • Maxwell, P., et al., “The Effectiveness of IDDQ, Functional, and Scan Tests: How Many Fault Coverages Do We Need?,” Proc. Int'l Test Conf., 1992, pp. 168-177.
    • (1992) Proc. Int'l Test Conf. , pp. 168-177
    • Maxwell, P.1
  • 7
    • 0041981521 scopus 로고
    • IDDQTesting in CMOS Digital ASICs: Putting It All Together
    • Perry, R., “IDDQTesting in CMOS Digital ASICs: Putting It All Together,” Proc. Int'l Test Conf., 1992, pp. 151-157.
    • (1992) Proc. Int'l Test Conf. , pp. 151-157
    • Perry, R.1
  • 8
    • 0027833778 scopus 로고
    • Fast and Accurate CMOS Bridging Fault Simulation
    • Rearick, J., and J. Patel, “Fast and Accurate CMOS Bridging Fault Simulation,” Proc. Int'l Test Conf., 1993, pp. 54-62.
    • (1993) Proc. Int'l Test Conf. , pp. 54-62
    • Rearick, J.1    Patel, J.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.