Can the current behavior of faulty and fault-free ICs and the impact on diagnosis

Proceedings - 1998 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 1998

Volumn 1998-December, Issue , 1998, Pages 202-210

  Thibeault, C ^a   Boisvert, L ^b  

^a ÉCOLE DE TECHNOLOGIE SUPÉRIEURE   (Canada)

^b Canadian Aviation Electronics Ltd   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

DEFECTS; FAULT TOLERANCE; INTEGRATED CIRCUITS; MAXIMUM LIKELIHOOD ESTIMATION; TIMING CIRCUITS; VLSI CIRCUITS;

BRIDGING FAULT; CURRENT BEHAVIORS; DIAGNOSIS METHODS; INTEGRATED CIRCUITS (ICS); SUB-THRESHOLD CURRENT;

FAULT DETECTION;

EID: 0343574644     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DFTVS.1998.732167     Document Type: Conference Paper

References (25)

1. IEEE Test Technology Technical Committee, "A D&T Roundtable: Deep-Submicron Test, " IEEE Design & Test of Computers, vol. 13, no. 3, Fall 1996, pp. 102-108.
2. E. Isern and J. Figueras, "IDDQ Test and Diagnosis of CMOS Circuits, " IEEE Design & Test of Computers, vol. 12, no. 4, Winter 1995, pp. 60-67.
3. R.C. Aitken, "Diagnosis of Leakage Faults with IDDQ, " J. Electronic Testing: Theory and Applications, vol. 3, no. 4, Dec. 1992, pp. 367-376.
4. R.C. Aitken, " Faults Location with Current Monitoring, " Proc. Intl Test Conf., 1991, pp. 623-623.
5. J.M. Soden and R.E. Anderson, "IC Failure Analysis: Techniques and Tool for Quality and Reliability Improvement, " Proc. IEEE, vol. 81, no. 5, May 1994, pp. 703-715.
6. T. Lee et al., "Circuit-Level Dictionaries of CMOS Bridging Faults, " IEEE VLSI Test Conf., 1994, pp. 386-391.
7. J.A. Waicukauski and E. Lindbloom, "Failure Diagnosis of Structured VLSI, " IEEE Design & Test of Computers, vol. 6, no. 4, Fall 1989, pp. 49-60.
8. S. Chakravarty and M. Liu, "Algorithms for IDDQ Measurement Based Diagnosis of Bridging Faults, " J. Electronic Testing: Theory and Applications, vol. 3, no. 4, Dec. 1992, pp. 377-386.
9. J.M. Soden, C.F. Hawkins, and A.C. Miller, "Identifying defects in deep-submicron CMOS ICs, " IEEE Spectrum, vol. 33, no. 9, Sept. 1996, pp. 66-71.
10. T. Williams, R. Dennard, R. Kapur, M, Mercer, and W. Maly, "Iddq Test: Sensitivity analysis of scaling, " in International Test Conference, pp. 786-792, October 1996.
11. J.G. Proakis, Digital Communications, Third Edition, McGraw-Hill, New-York, 1983.
12. A. Ferré and J. Figueras, "On Estimating Bounds of Quiescent Current for IDDQ testing, " Proc. IEEE VLSI Test Conference, 1996, pp. 106-111.
13. D. Josephson, M. Storey, and D. Dixon, "Microprocessor IDDQ Testing: A Case Study, " IEEE Design & Test of Computers, vol. 12, no. 2, Summer 1995, pp. 42-52.
14. A.E. Gattiker and W. Maly, "Current Signatures, " Proc. IEEE VLSI Test Conf., 1996, pp. 112-117.
15. F. Brglez and H. Fujiwara, "A Neutral Netlist of 10 Combinatorial Benchmark Circuits and a Target Translator in FORTRAN, " Proc. ISCAS, 1985, pp. 695-698.
16. Canadian Microelectronic Corporation, Guide to the Integrated Circuit Implementation Services of the Canadian Microelectronic Corporation, Queens University, Kingston, Ontario, CMC, 1990.
17. C. Thibeault, "A Novel Probabilistic Approach for IC Diagnosis Based on Differential Quiescent Current Signatures, " Proc. IEEE VLSI Test Conference, 1997, pp. 80-85.
18. C. Thibeault and L. Boisvert, "Diagnosis Method Based on D Iddq Probabilistic Signatures: Experimental Results, " accepted for publication at IEEE Intl Test Conf, 1998.
19. R. Rodriguez-Montanes, E.M.J.G. Bruls, and J. Figueras, " Bridging Defects Resistance Measurements in a CMOS Process, " Intl Test Conference, 1992, pp. 892-899.
20. A.H. Bowker and G.J. Lieberman, Engineering Statistics, Second Edition, Prentice-Hall, New Jersey, 1972.
21. S.M. Ross, Introduction to Probability Models, Third Edition, Academic Press, Orlando, Florida, 1985.
22. A.E. Gattiker and W. Maly, "Current Signatures: Application, " IEEE Intl Test Conf., 1997, pp. 156-165.
23. P. Nigh, W. Needham, K. Butler, P. Maxwell and R. Aitken, "An Experimental Study Comparing the Relative Effectiveness of Functional, Scan, Iddq, and Delay-Fault Testing, " IEEE VLSI Test Symp., 1997, pp. 459-463.
24. C. Thibeault, "Increasing current testing resolution, " accepted for publication at IEEE Intl Symp. on Defect and Fault Tolerance, 1998.
25. C. Thibeault, "Using Fourier analyses to enhance IC testability, " IEEE Intl Work. on Defect and Fault Tolerance, pp. 280-288, 1994.