IC failure analysis: Magic, mystery, and science

IEEE Design and Test of Computers

Volumn 14, Issue 3, 1997, Pages 59-69

  Soden, Jerry M ^a,b,c,d,h   Anderson, Richard E ^a,e,f   Henderson, Chris L ^a,c,g  

^a SANDIA NATIONAL LABORATORIES   (United States)

^b KANSAS STATE UNIVERSITY   (United States)

^c UNIVERSITY OF NEW MEXICO   (United States)

^d ITC Program Committee   (United States)

^e ITC Program Committee ^*  (United States)

^f UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

^g NEW MEXICO INSTITUTE OF MINING AND TECHNOLOGY   (United States)

^h SANDIA NATIONAL LABORATORIES   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER DEBUGGING; COMPUTER SIMULATION; COST EFFECTIVENESS; INTEGRATED CIRCUITS; MARKETING; OPTICAL MICROSCOPY; RELIABILITY; SCANNING ELECTRON MICROSCOPY; SCANNING TUNNELING MICROSCOPY; TRANSMISSION ELECTRON MICROSCOPY;

INTEGRATED CIRCUIT FAILURE ANALYSIS;

INTEGRATED CIRCUIT TESTING;

EID: 0031192065     PISSN: 07407475     EISSN: None     Source Type: Journal    
DOI: 10.1109/54.605998     Document Type: Article

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