High speed regenerator-section terminating LSI operating up to 2.5 Gbit/s using 0.5 μm Si bipolar standard-cell technology

Electronics Letters

Volumn 31, Issue 10, 1995, Pages 791-792

  Kawai, K ^a   Koike, K ^a   Ichino, H ^a   Kobayashi, Y ^a  

^a NTT CORPORATION   (Japan)

Author keywords

Bipolar integrated circuits; Large scale integration; Synchronous digital hierarchy

Indexed keywords

EID: 5244264281     PISSN: 00135194     EISSN: None     Source Type: Journal    
DOI: 10.1049/el:19950528     Document Type: Article

References (7)

1. KOIKE, K., KAWAI, K., and ICHINO, H.: ‘A design methodology of bipolar standard cell LSIs for Gbit/s signal processing’. Proc. IEEE 1993 Bipolar Circuits and Technol. Meeting, 1993, pp. 236-239
2. YAMAGUCHI, C., KOBAYASHI, Y., MIYAKE, M., ISHII, K., and ICHINO. H.: ‘0.5-μm bipolar technology using a new base formation method:SST1C’. Proc. IEEE 1993 Bipolar Circuits and Technol. Meeting, 1993. pp. 63-66
3. YAMABAYASHI, Y., MATSUOKA, S., UEMATSU, Y., HOHKAWA, K., and OHHATA, M.: ‘Line terminating multiplexers for SDH optical networks’, J. Lightwave Technol, 1993, LT-11, pp. 875-881
4. YAMABAYASHI, Y., SATO, Y., MATSUOKA, S., and HOHKAWA, K.: ‘High-Speed regenerator section terminating LSIs’. Electron. Lett., 1993, 29, pp. 2057-2058
5. HARADA, I., and KITAZAWA, H.: ‘A global router optimizing timing and area for high-speed bipolar LSIs’. IEEE Proc. 1994 31st Design Automation Conf., 1994, pp. 177-181
6. TAKEI, Y., HARADA, L., and KITAZAWA, H.: ‘Channel routing program for high-speed LSIs’. Proc. Information Processing Society of Japan DA Symp. 1993, 1993, pp. 45-8
7. KAWAI, K., KOIKE, K., and ICHINO, H.: ‘Improvement of wiring delay approximation’. Proc. 1993 IEICE Fall Conf., 1993, Vol. A-57