Optimization of Buffer Stages in Bipolar VLSI Systems

IEEE Journal of Solid-State Circuits

Volumn 27, Issue 7, 1992, Pages 1002-1013

  Konstadinidis, Georgios K ^a   Berger, Horst H ^a  

^a TECHNISCHE UNIVERSITÄT BERLIN   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRONIC CIRCUITS, BUFFER; INTEGRATED CIRCUITS, CMOS; LOGIC CIRCUITS, EMITTER COUPLED; SEMICONDUCTOR DEVICES, BIPOLAR;

BICMOS BUFFERS; BIPOLAR VLSI CIRCUITS; CASCODE ECL VLSI CIRCUITS;

INTEGRATED CIRCUITS, VLSI;

EID: 0026898340     PISSN: 00189200     EISSN: 1558173X     Source Type: Journal    
DOI: 10.1109/4.142595     Document Type: Article

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