-
1
-
-
0025492159
-
Silicon bipolar integrated circuits for multigigabit per second lightwave communications
-
Sept.
-
H. Rein, “Silicon bipolar integrated circuits for multigigabit per second lightwave communications,” IEEE J. Lightwave Technol., vol. LT-8, pp. 1371-1378, Sept. 1990.
-
(1990)
IEEE J. Lightwave Technol.
, vol.LT-8
, pp. 1371-1378
-
-
Rein, H.1
-
3
-
-
0024169419
-
Bipolar transistor scaling for minimum switching delay and energy dissipation
-
J. M. Stork, “Bipolar transistor scaling for minimum switching delay and energy dissipation,” IEDM Tech. Dig., pp. 550-553, 1988.
-
(1988)
IEDM Tech. Dig.
, pp. 550-553
-
-
Stork, J.M.1
-
4
-
-
0025208814
-
An analytical model for the determination of the transient response of CML and ECL gates
-
Jan.
-
M. Y. Ghannam et al., “An analytical model for the determination of the transient response of CML and ECL gates,” IEEE Trans. Electron Devices, vol. 37, pp. 191-201, Jan. 1990.
-
(1990)
IEEE Trans. Electron Devices
, vol.37
, pp. 191-201
-
-
Ghannam, M.Y.1
-
5
-
-
0026923446
-
Physical timing modeling for bipolar VLSI
-
Sept.
-
A. T. Yang and Y. Chang, “Physical timing modeling for bipolar VLSI,” IEEE J. Solid-State Circuits, vol. 27, pp. 1245-1254, Sept. 1992.
-
(1992)
IEEE J. Solid-State Circuits
, vol.27
, pp. 1245-1254
-
-
Yang, A.T.1
Chang, Y.2
-
6
-
-
0005383576
-
The method of estimating delay in switching circuits and the figure of merit of a switching transistor
-
Nov.
-
K. G. Ashar, “The method of estimating delay in switching circuits and the figure of merit of a switching transistor,” IEEE Trans. Electron Devices, vol. ED-11, pp. 497-506, Nov. 1964.
-
(1964)
IEEE Trans. Electron Devices
, vol.ED-11
, pp. 497-506
-
-
Ashar, K.G.1
-
7
-
-
0006686675
-
Propagation delay in high speed silicon bipolar and GaAs HBT digital circuits
-
P. K. Tien, “Propagation delay in high speed silicon bipolar and GaAs HBT digital circuits,” Int. J. High Speed Electronics, vol. 1, pp. 101-124, 1990.
-
(1990)
Int. J. High Speed Electronics
, vol.1
, pp. 101-124
-
-
Tien, P.K.1
-
8
-
-
0018505201
-
Bipolar transistor design for optimized power-delay logic circuits
-
Aug.
-
D. D. Tang and P. M. Solomon, “Bipolar transistor design for optimized power-delay logic circuits,” IEEE J. Solid-State Circuits, vol. SC-14, pp. 679-684, Aug. 1979.
-
(1979)
IEEE J. Solid-State Circuits
, vol.SC-14
, pp. 679-684
-
-
Tang, D.D.1
Solomon, P.M.2
-
9
-
-
0001451810
-
A propagation-delay expression and its application to the optimization of polysilicon emitter ECL processes
-
Feb.
-
E. F. Chor et al., “A propagation-delay expression and its application to the optimization of polysilicon emitter ECL processes,” IEEE J. Solid-State Circuits, vol. SC-23, pp. 251-259, Feb. 1988.
-
(1988)
IEEE J. Solid-State Circuits
, vol.SC-23
, pp. 251-259
-
-
Chor, E.F.1
-
10
-
-
0025419648
-
Accurate analytical delay expressions for ECL and CML circuits and their applications to optimizing high-speed bipolar circuits
-
Apr.
-
W. Fang et al., “Accurate analytical delay expressions for ECL and CML circuits and their applications to optimizing high-speed bipolar circuits,” IEEE J. Solid-State Circuits, vol. SC-25, pp. 572-583, Apr. 1990.
-
(1990)
IEEE J. Solid-State Circuits
, vol.SC-25
, pp. 572-583
-
-
Fang, W.1
-
11
-
-
0025474495
-
An analytical maximum toggle frequency expression and its application to optimizing high-speed ECL frequency dividers
-
Aug.
-
W. Fang et al., “An analytical maximum toggle frequency expression and its application to optimizing high-speed ECL frequency dividers,” IEEE J. Solid-State Circuits, vol. 25, pp. 920-930, Aug. 1990.
-
(1990)
IEEE J. Solid-State Circuits
, vol.25
, pp. 920-930
-
-
Fang, W.1
-
13
-
-
84939324432
-
Studies on the propagation delay time of high-speed CML/ECL bipolar circuit structures
-
Waterloo, Ont., Canada, Internal Rep.
-
K. M. Sharaf, “Studies on the propagation delay time of high-speed CML/ECL bipolar circuit structures,” Univ. Waterloo, Waterloo, Ont., Canada, Internal Rep., 1992.
-
(1992)
Univ. Waterloo
-
-
Sharaf, K.M.1
-
14
-
-
2442757838
-
Accurate delay models for digital BiCMOS
-
P. A. Raje et al., “Accurate delay models for digital BiCMOS,” IEEE Trans. Electron Devices, vol. 39, pp. 1456-1464, June 1992.
-
(1992)
IEEE Trans. Electron Devices
, vol.39
, pp. 1456-1464
-
-
Raje, P.A.1
-
15
-
-
0026820811
-
An accurate analytical BiCMOS delay expression and its application to optimizing high-speed BiCMOS circuits
-
Feb.
-
W. Fang et al., “An accurate analytical BiCMOS delay expression and its application to optimizing high-speed BiCMOS circuits,” IEEE J. Solid-State Circuits, vol. 27, pp. 191-202, Feb. 1992.
-
(1992)
IEEE J. Solid-State Circuits
, vol.27
, pp. 191-202
-
-
Fang, W.1
-
16
-
-
84939365758
-
A 1- μ m trench isolated high speed bipolar transistor
-
San Diego, CA
-
S. Duncan et al., “A 1- μ m trench isolated high speed bipolar transistor,” presented at the VLSI Symp., San Diego, CA, 1988.
-
(1988)
presented at the VLSI Symp.
-
-
Duncan, S.1
-
17
-
-
0023345330
-
High-speed frequency dividers using self-aligned AlGaAs/GaAs heterojunction bipolar transistors
-
T. Ishibashi et al., “High-speed frequency dividers using self-aligned AlGaAs/GaAs heterojunction bipolar transistors,” IEEE Electron Device Lett., vol. EDL-8, pp. 194-196, 1987.
-
(1987)
IEEE Electron Device Lett.
, vol.EDL-8
, pp. 194-196
-
-
Ishibashi, T.1
-
18
-
-
0023387537
-
22 GHz 1/4 frequency divider using AlGaAs/GaAs HBTs
-
Y. Yamauchi et al., “22 GHz 1/4 frequency divider using AlGaAs/GaAs HBTs,” Electron. Lett., vol. 23, pp. 881-882, 1987.
-
(1987)
Electron. Lett.
, pp. 881-882
-
-
Yamauchi, Y.1
-
19
-
-
84939325102
-
On the optimization of high-speed CML and ECL bipolar circuit structures
-
to be submitted
-
K. M. Sharaf and M. I. Elmasry, “On the optimization of high-speed CML and ECL bipolar circuit structures,” IEEE J. Comput.-Aided Design, to be submitted.
-
IEEE J. Comput.-Aided Design
-
-
Sharaf, K.M.1
Elmasry, M.I.2
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