Reliable tantalum-gate fully-depleted-soi mosfet technology featuring low-temperature processing

IEEE Transactions on Electron Devices

Volumn 44, Issue 9, 1997, Pages 1467-1472

  Ushiki, Takeo ^a   Yu, Mo Chiun ^a   Hirano, Yuichi ^a   Shimada, Hisayuki ^a   Morita, Mizuho ^a   Ohmi, Tadahiro ^a  

^a TOHOKU UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CRYSTALLIZATION; GATES (TRANSISTOR); SILICA; SILICON ON INSULATOR TECHNOLOGY; TANTALUM;

FULLY DEPLETED SILICON ON INSULATOR (FDSOI) DEVICES;

MOSFET DEVICES;

EID: 0031236185     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/16.622603     Document Type: Article

References (21)

1. J.P. Colinge, Silicon-on-Insulator Technology: Material to VLSI. Boston, MA: Kluwer, 1991.
2. M.J. Sherony, L. T. Su, J. E. Chung, and D. A. Antoniadis, "Reduction of threshold voltage sensitivity in SOI MOSFET's," IEEE Electron Device Lett., vol. 16, pp. 100-102, Mar. 1995.
3. G.G. Shahidi, C. Blair, K. Beyer, T. Bucelot, T. Buti, P. N. Chang, S. Chu, P. Coane, J. Comfort, B. Davari, R. Dennard, S. Furkay, H. Hovel, J. Johnson, D. Klaus, K. Kiewtniack, R. Logan, T. Lii, P. A. McFarland, N. Mazzeo, D. Moy, S. Neely, M. Rodriguez, D. Sadana, S. Stiffler, J. Sun, F. Swell, and J. Warnock, "A room temperature 0.1-μm CMOS on SOI," in Dig. Papers Symp. VLSI Technol., 1993, pp. 27-28.
4. H. Shimada, Y. Hirano, T. Ushiki, and T. Ohmi, "Threshold voltage adjustment in SOI MOSFET's by employing Tantalum for gate material," in IEDM Tech. Dig., 1995, pp. 881-884.
5. H. Shimada, T. Ushiki, Y. Hirano, and T. Ohmi, "Tantalum-gate SOI MOSFET's featuring threshold voltage control in low-power applications," in Proc. 1995 IEEE Int. SOI Conf., Tucson, AZ, 1995, pp. 96-97.
6. T. Ohno, Y. Kado, M. Harada, and T. Tsuchiya, "A high-performance ultra-thin quarter-micron CMOS/SIMOX technology," in Dig. Papers, Symp. VLSI Technol., 1993, pp. 25-26.
7. Y. Kado, T. Ohno, Y. Sakakibara, Y. Kawai, E. Yamamoto, A. Ohtaka, and T. Tsuchiya, "Dynamic performance and leakage current characteristics of 1/4-micron-gate ultra-thin CMOS/SIMOX gate array," in IEDM Tech. Dig., 1994, pp. 665-668.
8. L.T. Su, H. Hu, J. B. Jacobs, M. J. Sherony, A. Wei, and D. A. Antoniadis, "Tradeoffs of current drive vs. short-channel effect in deep-submicrometer bulk and SOI MOSFET's," in IEDM Tech. Dig., 1994, pp. 649-652.
9. 2 by dual-frequency-excitation plasma process," in Ext. Abstr. 181st Electrochem. Soc. Meet., St. Louis, MO, 1992, pp. 217-218.
10. H. Goto, M. Sasaki, T. Ohmi, T. Shibata, A. Yamagami, N. Okamura, and O. Kamiya, "Minimizing wafer surface damage and chamber material contamination in new plasma equipment," Jpn.J. Appl. Phys., vol. 29, pp. L2395-L2397, 1990.
11. H. Goto, M. Sasaki, T. Ohmi, T. Shibata, A. Yamagami, N. Okamura, and O. Kamiya, "A low damage, low contaminant plasma processing system utilizing energy clean technology," IEEE Trans. Semiconduct. Manufact., vol. 4, pp. 111-121, 1991.
12. H.D. Lowe, H. Goto, and T. Ohmi, "Control of ion energy and flux in a dual radio frequency excitation magnetron sputtering discharge," J. Vac. Sci. Technol., vol. A9, pp. 3090-3099, 1991.
13. A.E. Michel, F. F. Fang, and E. S. Pan, "Annealing properties of ion-implanted p-n junctions in silicon," J. Appl. Phys., vol. 45, pp. 2991-2996, 1974.
14. K. Tsukamoto, Y. Asakawa, Y. Watari, Y. Kusano, Y. Hirose, and G. Nakamura, "Arsenic-implanted emitter and its application to UHF power transistors," Jpn.J. Appl. Phys., vol. 17, pp. 187-192, 1978.
15. T. Ohmi, K. Masuda, H. Hashimoto, T. Shibata, M. Kato, and Y. Ishihara, "Formation of Arsenic-implanted pn junctions using high vacuum ion implanter," in Ext. Abstr. 19th Conf. Solid-State Dev. Mater., Aug. 1987, pp. 299-302.
16. Y. Ishihara, A. Okita, K. Yoshikawa, T. Shibata, T. Ohmi, T. Nitta, J. Sugiura, and N. Ohwada, "Reverse-bias current reduction in low-temperature-annealed pn junctions using a UHV ion-implanter," in Ext. Abstr. 21st Conf. Solid-State Dev. Mater., Aug. 1989, pp. 421-424.
17. S.W. Crowder, P. M. Rousseau, J. P. Snyder, J. A. Scott, P. B. Griffin, and J. D. Plummer, "The effect of source/drain processing on the reverse short channel effect of deep sub-micro bulk and SOI NMOSFET's," in IEDM Tech. Dig., 1995, pp. 427-430.
18. K. Tomita, T. Migita, S. Shimonishi, T. Shibata, T. Ohmi, and T. Nitta, "Eliminating metal-sputter contamination in ion implanter for low-temperature-annealed, low-reverse-bias-current junction," J. Electrochem. Soc., vol. 142, no. 5, pp. 1692-1698, 1995.
19. M. Yoshimi, H. Hazama, M. Takahashi, S. Kambayashi, T. Wada, K. Kato, and H. Tango, "Two-dimensional simulation and measurement of high-performance MOSFET's made on a very thin SOI film," IEEE Trans. Electron Devices, vol. 36, pp. 493-503, Mar. 1989.
20. L.T. Su, J. B. Jacobs, J. E. Chung, and D. A. Antoniadis, "Deep-submicrometer channel design in silicon-on-insulator (SOI) MOSFET's," IEEE Electron Device Lett., vol. 15, pp. 366-369, Sept. 1994.
21. Y. Omura, S. Nakashima, K. Izumi, and T. Ishii, "0.1-μm-gate, ultra-thin-film CMOS devices using SIMOX substrate with 80-nm thick buried oxide layer," in IEDM Tech. Dig., 1991, pp. 675-678.