A room temperature 0.1 μm CMOS on SOI

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 1993, Pages 27-28

  Shahidi, G G ^a   Blair, C ^a   Beyer, K ^a   Bucelot, T ^a   Buti, T ^a   Chang, P N ^a   Chu, S ^a   Coane, P ^a   Comfort, J ^a   Davari, B ^a   Dennard, R ^a   Furkay, S ^a   Hovel, H ^a   Johnson, J ^a   Klaus, D ^a   Kiewtniack, K ^a   Logan, R ^a   Lii, T ^a   McFarland, P A ^a   Mazzeo, N ^a   Moy, D ^a   Neely, S ^a   Ning, T ^a   Rodriguez, M ^a   Sadana, D ^a   Stiffler, S ^a   Sun, J ^a   Swell, F ^a   Warnock, J ^a   more..

^a IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

SEMICONDUCTOR DOPING; THRESHOLD VOLTAGE; VLSI CIRCUITS;

CHANNEL DOPINGS; CHANNEL LENGTH; CMOS TECHNOLOGY; NON-UNIFORM; SHORT-CHANNEL EFFECT; SOURCE-DRAIN EXTENSIONS;

CMOS INTEGRATED CIRCUITS;

EID: 84948608700     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSIT.1993.760228     Document Type: Conference Paper

References (3)

1. G. Shahidi. SSDM Tech. Dig., (1992) 56.
2. J. P. Colinge: "SO1 Technology", Kluwer Press, 1991.
3. G. Shahidi et al, Submitted to IEEE EDL.