Deep-Submicrometer Channel Design in Silicon-on-Insulator (SOI) MOSFET's

IEEE Electron Device Letters

Volumn 15, Issue 9, 1994, Pages 366-369

  Su, Lisa T ^a   Jacobs, Jarvis B ^a   Chung, James E ^a   Antoniadis, Dimitri A ^a  

^a MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

GATES (TRANSISTOR); NUMERICAL ANALYSIS; PRODUCT DESIGN; SEMICONDUCTOR DEVICE MANUFACTURE; SEMICONDUCTOR DEVICE MODELS; SEMICONDUCTOR DEVICE STRUCTURES; SEMICONDUCTOR DOPING; SEMICONDUCTOR JUNCTIONS; SILICON ON INSULATOR TECHNOLOGY; THIN FILM DEVICES;

CHARGE SHARING PHENOMENON; DEEP SUBMICROMETER CHANNEL DESIGN; SHORT CHANNEL EFFECTS;

MOSFET DEVICES;

EID: 0028499440     PISSN: 07413106     EISSN: 15580563     Source Type: Journal    
DOI: 10.1109/55.311136     Document Type: Article

References (9)

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9. G. Shahidi, C. Blair, K. Beyer, T. Bucelot, T. Buti, P. Chang, S. Chu, P. Coane, J. Comfort, B. Davari, R. Dennard, S. Furkay, H. Hovel, J. Johnson, D. Klaus, K. Kiewtniack, T. Lii, P. McFarland, N. Mazzeo, D. Moy, S. Nealy, T. Ning, M. Rodriguez, D. Sadana, S. Stiffler, J. Sun, F. Swell, and J. Warnock, “A room temperature 0.1 µm CMOS on SOI,” Tech. Dig. of Papers, VLSI Symp., pp. 92–93, 1993.