Reduction of threshold voltage sensitivity in SOI MOSFET's

IEEE Electron Device Letters

Volumn 16, Issue 3, 1995, Pages 100-102

  Sherony, Melanie J ^a   Chung, James E ^a   Antoniadis, Dimitri A ^a   Su, Lisa T ^b  

^a MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

^b TEXAS INSTRUMENTS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; MATHEMATICAL MODELS; MOS DEVICES; SEMICONDUCTING FILMS; SEMICONDUCTING SILICON; SEMICONDUCTOR DOPING; SUBSTRATES; THIN FILMS;

DRAIN INDUCED BARRIER LOWERING; ONE DIMENSIONAL PROCESS SIMULATIONS; REALISTIC PROCESS PARAMETERS; SHORT CHANNEL EFFECTS; THRESHOLD VOLTAGE SENSITIVITY;

MOSFET DEVICES;

EID: 0029277290     PISSN: 07413106     EISSN: 15580563     Source Type: Journal    
DOI: 10.1109/55.363235     Document Type: Article

References (4)

1. H.-K. Lim and J. Fossum, “Threshold voltage of thin-film silicon-on-insulator (SOI) MOSFET's,” IEEE Trans. Electron Devices, vol. ED-30, pp. 1244–1251, 1983.
2. J. B. McKitterick and A. T. Caviglia, “An analytical model for thin SOI transistors,” IEEE Trans. Electron Devices, vol. 36, pp. 1133–1138, 1989
3. L. T. Su, J. B. Jacobs J. E. Chung, and D. A. Antoniadis, “Short channel effects in deep-submicrometer SOI MOSFETS,” in IEEE Int. SOI Conf. Proc., 1993, pp. 112–113.
4. M. J. Sherony, L. T. Su, J. E. Chung, and D. A. Antoniadis, “Minimization of threshold voltage variation in SOI MOSFETS,” i n IEEE Int. SOI Conf. Proc., 1994, pp. 131–132.