A unified SOC test approach based on test data compression and TAM design

Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

Volumn 2003-January, Issue , 2003, Pages 511-518

  Iyengar, Vikram ^a   Chandra, Anshuman ^b  

^a IBM MICROELECTRONICS   (United States)

^b SYNOPSYS INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BENCHMARKING; DEFECTS; DESIGN FOR TESTABILITY; FAULT TOLERANCE; INTEGRATED CIRCUIT TESTING; SEQUENTIAL CIRCUITS;

RESOURCE REQUIREMENTS; TEST ACCESS MECHANISM; TEST APPLICATION TIME; TEST ARCHITECTURE; TEST DATA COMPRESSION; TEST DATA VOLUME REDUCTIONS; TEST METHODOLOGY; TEST-DATA VOLUME;

DATA COMPRESSION;

EID: 84964933288     PISSN: 15505774     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/TSM.2005.1250150     Document Type: Conference Paper

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