-
1
-
-
84867135575
-
Building high-level features using large scale unsupervised learning
-
Edinburgh, Scotland, Jun.
-
Q. V. Le, M. Ranzato, R. Monga, M. Devin, K. Chen, G. S. Corrado, J. Dean, and A. Y. Ng, "Building high-level features using large scale unsupervised learning," in Proc. ICML, Edinburgh, Scotland, Jun. 2012, pp. 81-88.
-
(2012)
Proc. ICML
, pp. 81-88
-
-
Le, Q.V.1
Ranzato, M.2
Monga, R.3
Devin, M.4
Chen, K.5
Corrado, G.S.6
Dean, J.7
Ng, A.Y.8
-
2
-
-
84866714584
-
Multi-column deep neural networks for image classification
-
Providence, RI, USA, Jun.
-
D. Ciresan, U. Meier, and J. Schmidhuber, "Multi-column deep neural networks for image classification," in Proc. CVPR, Providence, RI, USA, Jun. 2012, pp. 3642-3649.
-
(2012)
Proc. CVPR
, pp. 3642-3649
-
-
Ciresan, D.1
Meier, U.2
Schmidhuber, J.3
-
3
-
-
84883190472
-
Large scale distributed deep networks
-
Lake Tahoe, NV, USA, Dec.
-
J. Dean et al., "Large scale distributed deep networks," in Proc. NIPS, Lake Tahoe, NV, USA, Dec. 2012, pp. 1-9.
-
(2012)
Proc. NIPS
, pp. 1-9
-
-
Dean, J.1
-
5
-
-
85028212283
-
Now you can build Google's $1M artificial brain on the cheap
-
Jun.
-
D. Hernandez, "Now you can build Google's $1M artificial brain on the cheap," Wired, Jun. 2013, pp. 9-48.
-
(2013)
Wired
, pp. 9-48
-
-
Hernandez, D.1
-
6
-
-
0004135065
-
Efficient backprop
-
G. Montavon, G. B. Orr, and K.-R. Müller, Eds., 2nd ed. Heidelberg, Germany: Springer-Verlag
-
Y. A. Le Cun, L. Bottou, G. B. Orr, and K.-R. Müller, "Efficient backprop," in Neural Networks: Tricks of the Trade, G. Montavon, G. B. Orr, and K.-R. Müller, Eds., 2nd ed. Heidelberg, Germany: Springer-Verlag, 2012.
-
(2012)
Neural Networks: Tricks of the Trade
-
-
Le Cun, Y.A.1
Bottou, L.2
Orr, G.B.3
Müller, K.-R.4
-
7
-
-
78649481350
-
Artificial neural networks in hardware: A survey of two decades of progress
-
Dec.
-
J. Misra and I. Saha, "Artificial neural networks in hardware: A survey of two decades of progress," Neurocomputing, vol. 74, nos. 1-3, pp. 239-255, Dec. 2010.
-
(2010)
Neurocomputing
, vol.74
, Issue.1-3
, pp. 239-255
-
-
Misra, J.1
Saha, I.2
-
8
-
-
0034570060
-
Neurocomputers: A dead end?
-
A. R. Omondi, "Neurocomputers: A dead end?" Int. J. Neural Syst., vol. 10, no. 6, pp. 475-481, 2000.
-
(2000)
Int. J. Neural Syst.
, vol.10
, Issue.6
, pp. 475-481
-
-
Omondi, A.R.1
-
9
-
-
78649765239
-
The brain of a new machine
-
Dec.
-
M. Versace and B. Chandler, "The brain of a new machine," IEEE Spectr., vol. 47, no. 12, pp. 30-37, Dec. 2010.
-
(2010)
IEEE Spectr.
, vol.47
, Issue.12
, pp. 30-37
-
-
Versace, M.1
Chandler, B.2
-
10
-
-
84887388670
-
Neuroelectronics: Smart connections
-
Nov.
-
M. M. Waldrop, "Neuroelectronics: Smart connections," Nature, vol. 503, no. 7474, pp. 22-24, Nov. 2013.
-
(2013)
Nature
, vol.503
, Issue.7474
, pp. 22-24
-
-
Waldrop, M.M.1
-
11
-
-
0015127532
-
Memristor-The missing circuit element
-
Sep.
-
L. O. Chua, "Memristor-the missing circuit element," IEEE Trans. Circuit Theory, vol. 18, no. 5, pp. 507-519, Sep. 1971.
-
(1971)
IEEE Trans. Circuit Theory
, vol.18
, Issue.5
, pp. 507-519
-
-
Chua, L.O.1
-
12
-
-
43049126833
-
The missing memristor found
-
Mar.
-
D. B. Strukov, G. S. Snider, D. R. Stewart, and R. S. Williams, "The missing memristor found," Nature, vol. 453, no. 7191, pp. 80-83, Mar. 2008.
-
(2008)
Nature
, vol.453
, Issue.7191
, pp. 80-83
-
-
Strukov, D.B.1
Snider, G.S.2
Stewart, D.R.3
Williams, R.S.4
-
13
-
-
84863705823
-
A boundary condition-based approach to the modeling of memristor nanostructures
-
Nov.
-
F. Corinto and A. Ascoli, "A boundary condition-based approach to the modeling of memristor nanostructures," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 59, no. 11, pp. 2713-2726, Nov. 2012.
-
(2012)
IEEE Trans. Circuits Syst. I, Reg. Papers
, vol.59
, Issue.11
, pp. 2713-2726
-
-
Corinto, F.1
Ascoli, A.2
-
14
-
-
84872100046
-
TEAM: Threshold adaptive memristor model
-
Jan.
-
S. Kvatinsky, E. G. Friedman, A. Kolodny, and U. C. Weiser, "TEAM: Threshold adaptive memristor model," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 60, no. 1, pp. 211-221, Jan. 2013.
-
(2013)
IEEE Trans. Circuits Syst. I, Reg. Papers
, vol.60
, Issue.1
, pp. 211-221
-
-
Kvatinsky, S.1
Friedman, E.G.2
Kolodny, A.3
Weiser, U.C.4
-
15
-
-
84910060968
-
Memristor-based multithreading
-
Jul.
-
S. Kvatinsky, Y. H. Nacson, Y. Etsion, E. G. Friedman, A. Kolodny, and U. C. Weiser, "Memristor-based multithreading," Comput. Archit. Lett., vol. 13, no. 1, pp. 41-44, Jul. 2014.
-
(2014)
Comput. Archit. Lett.
, vol.13
, Issue.1
, pp. 41-44
-
-
Kvatinsky, S.1
Nacson, Y.H.2
Etsion, Y.3
Friedman, E.G.4
Kolodny, A.5
Weiser, U.C.6
-
16
-
-
84908090755
-
Passivity and passification of memristorbased recurrent neural networks with time-varying delays
-
Nov.
-
Z. Guo, J. Wang, and Z. Yan, "Passivity and passification of memristorbased recurrent neural networks with time-varying delays," IEEE Trans. Neural Netw. Learn. Syst., vol. 25, no. 11, pp. 2099-2109, Nov. 2014.
-
(2014)
IEEE Trans. Neural Netw. Learn. Syst.
, vol.25
, Issue.11
, pp. 2099-2109
-
-
Guo, Z.1
Wang, J.2
Yan, Z.3
-
17
-
-
84943795368
-
Adaptive synchronization of memristor-based neural networks with time-varying delays
-
to be published
-
L. Wang, Y. Shen, Q. Yin, and G. Zhang, "Adaptive synchronization of memristor-based neural networks with time-varying delays," IEEE Trans. Neural Netw. Learn. Syst., to be published.
-
IEEE Trans. Neural Netw. Learn. Syst.
-
-
Wang, L.1
Shen, Y.2
Yin, Q.3
Zhang, G.4
-
18
-
-
84897450409
-
Exponential synchronization of delayed memristor-based chaotic neural networks via periodically intermittent control
-
Jul.
-
G. Zhang and Y. Shen, "Exponential synchronization of delayed memristor-based chaotic neural networks via periodically intermittent control," Neural Netw., vol. 55, pp. 1-10, Jul. 2014.
-
(2014)
Neural Netw.
, vol.55
, pp. 1-10
-
-
Zhang, G.1
Shen, Y.2
-
19
-
-
80054729052
-
Simulation of a memristorbased spiking neural network immune to device variations
-
San Jose, CA, USA, Jul./Aug.
-
D. Querlioz, O. Bichler, and C. Gamrat, "Simulation of a memristorbased spiking neural network immune to device variations," in Proc. Int. Joint Conf. Neural Netw. (IJCNN), San Jose, CA, USA, Jul./Aug. 2011, pp. 1775-1781.
-
(2011)
Proc. Int. Joint Conf. Neural Netw. (IJCNN)
, pp. 1775-1781
-
-
Querlioz, D.1
Bichler, O.2
Gamrat, C.3
-
20
-
-
84860660887
-
On spike-timing-dependent-plasticity, memristive devices, and building a self-learning visual cortex
-
Jan.
-
C. Zamarreño-Ramos, L. A. Camuñas-Mesa, J. A. Pérez-Carrasco, T. Masquelier, T. Serrano-Gotarredona, and B. Linares-Barranco, "On spike-timing-dependent-plasticity, memristive devices, and building a self-learning visual cortex," Frontiers Neurosci., vol. 5, p. 26, Jan. 2011.
-
(2011)
Frontiers Neurosci
, vol.5
, pp. 26
-
-
Zamarreño-Ramos, C.1
Camuñas-Mesa, L.A.2
Pérez-Carrasco, J.A.3
Masquelier, T.4
Serrano-Gotarredona, T.5
Linares-Barranco, B.6
-
21
-
-
84863265567
-
Memristor-based synaptic networks and logical operations using in-situ computing
-
Adelaide, SA, Australia, Dec.
-
O. Kavehei et al., "Memristor-based synaptic networks and logical operations using in-situ computing," in Proc. 7th Int. Conf. Intell. Sensors, Sensor Netw. Inf. Process., Adelaide, SA, Australia, Dec. 2011, pp. 137-142.
-
(2011)
Proc. 7th Int. Conf. Intell. Sensors, Sensor Netw. Inf. Process
, pp. 137-142
-
-
Kavehei, O.1
-
22
-
-
84872029626
-
A neuromorphic architecture for object recognition and motion anticipation using burst-STDP
-
Jan.
-
A. Nere, U. Olcese, D. Balduzzi, and G. Tononi, "A neuromorphic architecture for object recognition and motion anticipation using burst-STDP," PloS One, vol. 7, no. 5, p. e36958, Jan. 2012.
-
(2012)
PloS One
, vol.7
, Issue.5
, pp. e36958
-
-
Nere, A.1
Olcese, U.2
Balduzzi, D.3
Tononi, G.4
-
23
-
-
84872510545
-
A digital neuromorphic VLSI architecture with memristor crossbar synaptic array for machine learning
-
Niagara Falls, NY, USA, Sep.
-
Y. Kim, Y. Zhang, and P. Li, "A digital neuromorphic VLSI architecture with memristor crossbar synaptic array for machine learning," in Proc. IEEE Int. SOC Conf. (SOCC), Niagara Falls, NY, USA, Sep. 2012, pp. 328-333.
-
(2012)
Proc. IEEE Int. SOC Conf. (SOCC)
, pp. 328-333
-
-
Kim, Y.1
Zhang, Y.2
Li, P.3
-
24
-
-
84865084960
-
Spike timing dependent plasticity with memristive synapse in neuromorphic systems
-
Brisbane, QLD, Australia, Jun.
-
W. Chan and J. Lohn, "Spike timing dependent plasticity with memristive synapse in neuromorphic systems," in Proc. Int. Joint Conf. Neural Netw. (IJCNN), Brisbane, QLD, Australia, Jun. 2012, pp. 1-6.
-
(2012)
Proc. Int. Joint Conf. Neural Netw. (IJCNN)
, pp. 1-6
-
-
Chan, W.1
Lohn, J.2
-
25
-
-
84878952572
-
STDP and STDP variations with memristors for spiking neuromorphic learning systems
-
Jan.
-
T. Serrano-Gotarredona, T. Masquelier, T. Prodromakis, G. Indiveri, and B. Linares-Barranco, "STDP and STDP variations with memristors for spiking neuromorphic learning systems," Frontiers Neurosci., vol. 7, p. 2, Jan. 2013.
-
(2013)
Frontiers Neurosci
, vol.7
, pp. 2
-
-
Serrano-Gotarredona, T.1
Masquelier, T.2
Prodromakis, T.3
Indiveri, G.4
Linares-Barranco, B.5
-
26
-
-
84877850976
-
Immunity to device variations in a spiking neural network with memristive nanodevices
-
May
-
D. Querlioz, O. Bichler, P. Dollfus, and C. Gamrat, "Immunity to device variations in a spiking neural network with memristive nanodevices," IEEE Trans. Nanotechnol., vol. 12, no. 3, pp. 288-295, May 2013.
-
(2013)
IEEE Trans. Nanotechnol
, vol.12
, Issue.3
, pp. 288-295
-
-
Querlioz, D.1
Bichler, O.2
Dollfus, P.3
Gamrat, C.4
-
27
-
-
25144452832
-
What can a neuron learn with spike-timing-dependent plasticity?
-
Mar.
-
R. Legenstein, C. Naeger, and W. Maass, "What can a neuron learn with spike-timing-dependent plasticity?" Neural Comput., vol. 17, no. 11, pp. 2337-2382, Mar. 2005.
-
(2005)
Neural Comput.
, vol.17
, Issue.11
, pp. 2337-2382
-
-
Legenstein, R.1
Naeger, C.2
Maass, W.3
-
28
-
-
79961199396
-
Robust neural logic block (NLB) based on memristor crossbar array
-
San Diego, CA, USA, Jun.
-
D. Chabi, W. Zhao, D. Querlioz, and J.-O. Klein, "Robust neural logic block (NLB) based on memristor crossbar array," in Proc. IEEE/ACM Int. Symp. IEEE Nanosc. Archit. (NANOARCH), San Diego, CA, USA, Jun. 2011, pp. 137-143.
-
(2011)
Proc. IEEE/ACM Int. Symp. IEEE Nanosc. Archit. (NANOARCH)
, pp. 137-143
-
-
Chabi, D.1
Zhao, W.2
Querlioz, D.3
Klein, J.-O.4
-
29
-
-
84860883459
-
Stochastic gradient descent inspired training technique for a CMOS/nano memristive trainable threshold gate array
-
May
-
H. Manem, J. Rajendran, and G. S. Rose, "Stochastic gradient descent inspired training technique for a CMOS/nano memristive trainable threshold gate array," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 59, no. 5, pp. 1051-1060, May 2012.
-
(2012)
IEEE Trans. Circuits Syst. I, Reg. Papers
, vol.59
, Issue.5
, pp. 1051-1060
-
-
Manem, H.1
Rajendran, J.2
Rose, G.S.3
-
30
-
-
84880141989
-
Memristor-based neural logic blocks for nonlinearly separable functions
-
Aug.
-
M. Soltiz, D. Kudithipudi, C. Merkel, G. S. Rose, and R. E. Pino, "Memristor-based neural logic blocks for nonlinearly separable functions," IEEE Trans. Comput., vol. 62, no. 8, pp. 1597-1606, Aug. 2013.
-
(2013)
IEEE Trans. Comput.
, vol.62
, Issue.8
, pp. 1597-1606
-
-
Soltiz, M.1
Kudithipudi, D.2
Merkel, C.3
Rose, G.S.4
Pino, R.E.5
-
31
-
-
84896979826
-
Pattern classification by memristive crossbar circuits usingex situ and in situ training
-
May
-
F. Alibart, E. Zamanidoost, and D. B. Strukov, "Pattern classification by memristive crossbar circuits usingex situ and in situ training," Nature Commun., vol. 4, p. 2072, May 2013.
-
(2013)
Nature Commun.
, vol.4
, pp. 2072
-
-
Alibart, F.1
Zamanidoost, E.2
Strukov, D.B.3
-
32
-
-
11144273669
-
The perceptron: A probabilistic model for information storage and organization in the brain
-
Nov.
-
F. Rosenblatt, "The perceptron: A probabilistic model for information storage and organization in the brain," Psychol. Rev., vol. 65, no. 6, pp. 386-408, Nov. 1958.
-
(1958)
Psychol. Rev.
, vol.65
, Issue.6
, pp. 386-408
-
-
Rosenblatt, F.1
-
33
-
-
0024861871
-
Approximation by superpositions of a sigmoidal function
-
G. Cybenko, "Approximation by superpositions of a sigmoidal function," Math. Control, Signals, Syst., vol. 2, no. 4, pp. 303-314, 1989.
-
(1989)
Math. Control, Signals, Syst.
, vol.2
, Issue.4
, pp. 303-314
-
-
Cybenko, G.1
-
34
-
-
84882309474
-
The tradeoffs of large scale learning
-
S. Sra, S. Nowozin, and S. J. Wright, Eds. Cambridge, MA, USA: MIT Press
-
L. Bottou and O. Bousquet, "The tradeoffs of large scale learning," in Optimization for Machine Learning, S. Sra, S. Nowozin, and S. J. Wright, Eds. Cambridge, MA, USA: MIT Press, 2011, p. 351.
-
(2011)
Optimization for Machine Learning
, pp. 351
-
-
Bottou, L.1
Bousquet, O.2
-
35
-
-
78649669320
-
Deep, big, simple neural nets for handwritten digit recognition
-
Nov.
-
D. Cireşan and U. Meier, "Deep, big, simple neural nets for handwritten digit recognition," Neural Comput., vol. 22, no. 12, pp. 3207-3220, Nov. 2010.
-
(2010)
Neural Comput.
, vol.22
, Issue.12
, pp. 3207-3220
-
-
Cireşan, D.1
Meier, U.2
-
36
-
-
84876895659
-
Memristor bridge synapse-based neural network and its learning
-
Sep.
-
S. P. Adhikari, C. Yang, H. Kim, and L. O. Chua, "Memristor bridge synapse-based neural network and its learning," IEEE Trans. Neural Netw. Learn. Syst., vol. 23, no. 9, pp. 1426-1435, Sep. 2012.
-
(2012)
IEEE Trans. Neural Netw. Learn. Syst.
, vol.23
, Issue.9
, pp. 1426-1435
-
-
Adhikari, S.P.1
Yang, C.2
Kim, H.3
Chua, L.O.4
-
37
-
-
84908469042
-
Enabling back propagation training of memristor crossbar neuromorphic processors
-
Beijing, China, Jul.
-
R. Hasan and T. M. Taha, "Enabling back propagation training of memristor crossbar neuromorphic processors," in Proc. Int. Joint Conf. Neural Netw. (IJCNN), Beijing, China, Jul. 2014, pp. 21-28.
-
(2014)
Proc. Int. Joint Conf. Neural Netw. (IJCNN)
, pp. 21-28
-
-
Hasan, R.1
Taha, T.M.2
-
38
-
-
80054733639
-
Review of stability properties of neural plasticity rules for implementation on memristive neuromorphic hardware
-
San Jose, CA, USA, Jul./Aug.
-
Z. Vasilkoski et al., "Review of stability properties of neural plasticity rules for implementation on memristive neuromorphic hardware," in Proc. Int. Joint Conf. Neural Netw., San Jose, CA, USA, Jul./Aug. 2011, pp. 2563-2569.
-
(2011)
Proc. Int. Joint Conf. Neural Netw.
, pp. 2563-2569
-
-
Vasilkoski, Z.1
-
40
-
-
0016918810
-
Memristive devices and systems
-
Feb.
-
L. O. Chua and S. M. Kang, "Memristive devices and systems," Proc. IEEE, vol. 64, no. 2, pp. 209-223, Feb. 1976.
-
(1976)
Proc. IEEE
, vol.64
, Issue.2
, pp. 209-223
-
-
Chua, L.O.1
Kang, S.M.2
-
41
-
-
70350092588
-
Switching dynamics in titanium dioxide memristive devices
-
M. D. Pickett et al., "Switching dynamics in titanium dioxide memristive devices," J. Appl. Phys., vol. 106, no. 7, p. 074508, 2009.
-
(2009)
J. Appl. Phys.
, vol.106
, Issue.7
, pp. 074508
-
-
Pickett, M.D.1
-
42
-
-
84879990023
-
State dynamics and modeling of tantalum oxide memristors
-
Jul.
-
J. Strachan et al., "State dynamics and modeling of tantalum oxide memristors," IEEE Trans. Electron Devices, vol. 60, no. 7, pp. 2194-2202, Jul. 2013.
-
(2013)
IEEE Trans. Electron Devices
, vol.60
, Issue.7
, pp. 2194-2202
-
-
Strachan, J.1
-
43
-
-
0002278965
-
-
Stanford Electron. Labs, Stanford Univ., Stanford, CA, USA, Tech. Rep
-
B. Widrow and M. E. Hoff, "Adaptive switching circuits," Stanford Electron. Labs, Stanford Univ., Stanford, CA, USA, Tech. Rep., 1960.
-
(1960)
Adaptive Switching Circuits
-
-
Widrow, B.1
Hoff, M.E.2
-
45
-
-
0020464111
-
Simplified neuron model as a principal component analyzer
-
Nov.
-
E. Oja, "Simplified neuron model as a principal component analyzer," J. Math. Biol., vol. 15, no. 3, pp. 267-273, Nov. 1982.
-
(1982)
J. Math. Biol.
, vol.15
, Issue.3
, pp. 267-273
-
-
Oja, E.1
-
47
-
-
79952748054
-
Pegasos: Primal estimated sub-gradient solver for SVM
-
Oct.
-
S. Shalev-Shwartz, Y. Singer, N. Srebro, and A. Cotter, "Pegasos: Primal estimated sub-gradient solver for SVM," Math. Program., vol. 127, no. 1, pp. 3-30, Oct. 2010.
-
(2010)
Math. Program.
, vol.127
, Issue.1
, pp. 3-30
-
-
Shalev-Shwartz, S.1
Singer, Y.2
Srebro, N.3
Cotter, A.4
-
48
-
-
84907607096
-
Memristor-based material implication (IMPLY) logic: Design principles and methodologies
-
Oct.
-
S. Kvatinsky, N. Wald, E. Satat, E. G. Friedman, A. Kolodny, and U. C. Weiser, "Memristor-based material implication (IMPLY) logic: Design principles and methodologies," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 22, no. 10, pp. 2054-2066, Oct. 2014.
-
(2014)
IEEE Trans. Very Large Scale Integr. (VLSI) Syst.
, vol.22
, Issue.10
, pp. 2054-2066
-
-
Kvatinsky, S.1
Wald, N.2
Satat, E.3
Friedman, E.G.4
Kolodny, A.5
Weiser, U.C.6
-
50
-
-
0032185581
-
Analog versus digital: Extrapolating from electronics to neurobiology
-
Oct.
-
R. Sarpeshkar, "Analog versus digital: Extrapolating from electronics to neurobiology," Neural Comput., vol. 10, no. 7, pp. 1601-1638, Oct. 1998.
-
(1998)
Neural Comput.
, vol.10
, Issue.7
, pp. 1601-1638
-
-
Sarpeshkar, R.1
-
51
-
-
84882383792
-
-
[Online]. accessed Nov. 21
-
The Mosis Service. [Online]. Available: http://www.mosis.com, accessed Nov. 21, 2012.
-
(2012)
The Mosis Service
-
-
-
52
-
-
35348843366
-
Compact physical models for power supply noise and chip/package co-design of gigascale integration
-
Sparks, NV, USA, May/Jun.
-
G. Huang, D. C. Sekar, A. Naeemi, K. Shakeri, and J. D. Meindl, "Compact physical models for power supply noise and chip/package co-design of gigascale integration," in Proc. IEEE 57th Electron. Compon. Technol. Conf. (ECTC), Sparks, NV, USA, May/Jun. 2007, pp. 1659-1666.
-
(2007)
Proc. IEEE 57th Electron. Compon. Technol. Conf. (ECTC)
, pp. 1659-1666
-
-
Huang, G.1
Sekar, D.C.2
Naeemi, A.3
Shakeri, K.4
Meindl, J.D.5
-
53
-
-
79952966334
-
2 thin-film and spintronic memristors
-
Yokohama, Japan, Jan.
-
2 thin-film and spintronic memristors," in Proc. 16th Asia South Pacific Design Autom. Conf., Yokohama, Japan, Jan. 2011, pp. 25-30.
-
(2011)
Proc. 16th Asia South Pacific Design Autom. Conf.
, pp. 25-30
-
-
Hu, M.1
Li, H.2
Chen, Y.3
Wang, X.4
Pino, R.E.5
-
54
-
-
85028197512
-
-
[Online]. accessed Nov. 21
-
Sim Electronics. [Online]. Available: http://www.mathworks.com/products/simelectronics/, accessed Nov. 21, 2012.
-
(2012)
Sim Electronics
-
-
-
55
-
-
79959342648
-
Synaptic behaviors and modeling of a metal oxide memristive device
-
Feb.
-
T. Chang, S.-H. Jo, K.-H. Kim, P. Sheridan, S. Gaba, and W. Lu, "Synaptic behaviors and modeling of a metal oxide memristive device," Appl. Phys. A, vol. 102, no. 4, pp. 857-863, Feb. 2011.
-
(2011)
Appl. Phys. A
, vol.102
, Issue.4
, pp. 857-863
-
-
Chang, T.1
Jo, S.-H.2
Kim, K.-H.3
Sheridan, P.4
Gaba, S.5
Lu, W.6
-
57
-
-
84945900998
-
Best practices for convolutional neural networks applied to visual document analysis
-
Edinburgh, Scotland, Aug.
-
P. Y. Simard, D. Steinkraus, and J. C. Platt, "Best practices for convolutional neural networks applied to visual document analysis," in Proc. 7th Int. Conf. Document Anal. Recognit., vol. 1. Edinburgh, Scotland, Aug. 2003, pp. 958-963.
-
(2003)
Proc. 7th Int. Conf. Document Anal. Recognit.
, vol.1
, pp. 958-963
-
-
Simard, P.Y.1
Steinkraus, D.2
Platt, J.C.3
-
58
-
-
84886655497
-
Reconfigurable nano-crossbar architectures
-
R. Waser, Ed. New York, NY, USA: Wiley
-
D. B. Strukov and K. K. Likharev, "Reconfigurable nano-crossbar architectures," in Nanoelectronics and Information Technology, R. Waser, Ed. New York, NY, USA: Wiley, 2012, pp. 543-562.
-
(2012)
Nanoelectronics and Information Technology
, pp. 543-562
-
-
Strukov, D.B.1
Likharev, K.K.2
-
59
-
-
0026866964
-
Analysis and verification of an analog VLSI incremental outer-product learning system
-
May
-
G. Cauwenberghs, C. F. Neugebauer, and A. Yariv, "Analysis and verification of an analog VLSI incremental outer-product learning system," IEEE Trans. Neural Netw., vol. 3, no. 3, pp. 488-497, May 1992.
-
(1992)
IEEE Trans. Neural Netw.
, vol.3
, Issue.3
, pp. 488-497
-
-
Cauwenberghs, G.1
Neugebauer, C.F.2
Yariv, A.3
-
60
-
-
0026106083
-
Hebbian plasticity in MOS synapses
-
Feb.
-
H. C. Card, C. R. Schneider, and W. R. Moore, "Hebbian plasticity in MOS synapses," IEE Proc. F, Radar Signal Process., vol. 138, no. 1, pp. 13-16, Feb. 1991.
-
(1991)
IEE Proc. F, Radar Signal Process
, vol.138
, Issue.1
, pp. 13-16
-
-
Card, H.C.1
Schneider, C.R.2
Moore, W.R.3
-
61
-
-
0026140324
-
Analogue CMOS Hebbian synapses
-
Apr.
-
C. Schneider and H. Card, "Analogue CMOS Hebbian synapses," Electron. Lett., vol. 27, no. 9, pp. 785-786, Apr. 1991.
-
(1991)
Electron. Lett.
, vol.27
, Issue.9
, pp. 785-786
-
-
Schneider, C.1
Card, H.2
-
62
-
-
0028751787
-
Learning capacitive weights in analog CMOS neural networks
-
Oct.
-
H. C. Card, C. R. Schneider, and R. S. Schneider, "Learning capacitive weights in analog CMOS neural networks," J. VLSI Signal Process. Syst. Signal, Image Video Technol., vol. 8, no. 3, pp. 209-225, Oct. 1994.
-
(1994)
J. VLSI Signal Process. Syst. Signal, Image Video Technol.
, vol.8
, Issue.3
, pp. 209-225
-
-
Card, H.C.1
Schneider, C.R.2
Schneider, R.S.3
-
63
-
-
0030122857
-
An experimental analog VLSI neural network with on-chip back-propagation learning
-
Apr.
-
M. Valle, D. D. Caviglia, and G. M. Bisio, "An experimental analog VLSI neural network with on-chip back-propagation learning," Analog Integr. Circuits Signal Process., vol. 9, no. 3, pp. 231-245, Apr. 1996.
-
(1996)
Analog Integr. Circuits Signal Process
, vol.9
, Issue.3
, pp. 231-245
-
-
Valle, M.1
Caviglia, D.D.2
Bisio, G.M.3
-
64
-
-
0028495068
-
An all-analog expandable neural network LSI with on-chip backpropagation learning
-
Sep.
-
T. Morie and Y. Amemiya, "An all-analog expandable neural network LSI with on-chip backpropagation learning," IEEE J. Solid-State Circuits, vol. 29, no. 9, pp. 1086-1093, Sep. 1994.
-
(1994)
IEEE J. Solid-State Circuits
, vol.29
, Issue.9
, pp. 1086-1093
-
-
Morie, T.1
Amemiya, Y.2
-
65
-
-
0036534928
-
An on-chip BP learning neural network with ideal neuron characteristics and learning rate adaptation
-
Apr.
-
C. Lu, B.-X. Shi, and L. Chen, "An on-chip BP learning neural network with ideal neuron characteristics and learning rate adaptation," Analog Integr. Circuits Signal Process., vol. 31, no. 1, pp. 55-62, Apr. 2002.
-
(2002)
Analog Integr. Circuits Signal Process
, vol.31
, Issue.1
, pp. 55-62
-
-
Lu, C.1
Shi, B.-X.2
Chen, L.3
-
66
-
-
0026998980
-
Neuro chips with on-chip back-propagation and/or Hebbian learning
-
Dec.
-
T. Shima, T. Kimura, Y. Kamatani, T. Itakura, Y. Fujita, and T. Iida, "Neuro chips with on-chip back-propagation and/or Hebbian learning," IEEE J. Solid-State Circuits, vol. 27, no. 12, pp. 1868-1876, Dec. 1992.
-
(1992)
IEEE J. Solid-State Circuits
, vol.27
, Issue.12
, pp. 1868-1876
-
-
Shima, T.1
Kimura, T.2
Kamatani, Y.3
Itakura, T.4
Fujita, Y.5
Iida, T.6
-
67
-
-
40649110894
-
Survey of neural network hardware
-
Apr.
-
C. S. Lindsey and T. Lindblad, "Survey of neural network hardware," Proc. SPIE, vol. 2492, pp. 1194-1205, Apr. 1995.
-
(1995)
Proc. SPIE
, vol.2492
, pp. 1194-1205
-
-
Lindsey, C.S.1
Lindblad, T.2
-
68
-
-
0038642931
-
A learning analog neural network chip with continuous-time recurrent dynamics
-
Golden, CO, USA, Nov.
-
G. Cauwenberghs, "A learning analog neural network chip with continuous-time recurrent dynamics," in Proc. NIPS, Golden, CO, USA, Nov. 1994, pp. 858-865.
-
(1994)
Proc. NIPS
, pp. 858-865
-
-
Cauwenberghs, G.1
-
69
-
-
0026401361
-
Neural network LSI chip with on-chip learning
-
Seattle, WA, USA, Jul.
-
H. Eguchi, T. Furuta, H. Horiguchi, S. Oteki, and T. Kitaguchi, "Neural network LSI chip with on-chip learning," in Proc. Int. Joint Conf. Neural Netw. (IJCNN), Seattle, WA, USA, Jul. 1991, pp. 453-456.
-
(1991)
Proc. Int. Joint Conf. Neural Netw. (IJCNN)
, pp. 453-456
-
-
Eguchi, H.1
Furuta, T.2
Horiguchi, H.3
Oteki, S.4
Kitaguchi, T.5
-
70
-
-
0026386918
-
CMOS implementation of analog Hebbian synaptic learning circuits
-
Seattle, WA, USA Jul.
-
C. Schneider and H. Card, "CMOS implementation of analog Hebbian synaptic learning circuits," in Proc. Int. Joint Conf. Neural Netw. (IJCNN), vol. i. Seattle, WA, USA, vol. 1, Jul. 1991, pp. 437-442.
-
(1991)
Proc. Int. Joint Conf. Neural Netw. (IJCNN)
, vol.1
, pp. 437-442
-
-
Schneider, C.1
Card, H.2
-
71
-
-
84856173450
-
High precision tuning of state for memristive devices by adaptable variation-tolerant algorithm
-
Feb.
-
F. Alibart, L. Gao, B. D. Hoskins, and D. B. Strukov, "High precision tuning of state for memristive devices by adaptable variation-tolerant algorithm," Nanotechnology, vol. 23, no. 7, p. 075201, Feb. 2012.
-
(2012)
Nanotechnology
, vol.23
, Issue.7
, pp. 075201
-
-
Alibart, F.1
Gao, L.2
Hoskins, B.D.3
Strukov, D.B.4
-
72
-
-
84937908919
-
Expectation backpropagation: Parameter-free training of multilayer neural networks with continuous or discrete weights
-
Montreal, QC, Canada, Dec.
-
D. Soudry, I. Hubara, and R. Meir, "Expectation backpropagation: Parameter-free training of multilayer neural networks with continuous or discrete weights," in Proc. NIPS, Montreal, QC, Canada, Dec. 2014, pp. 963-971.
-
(2014)
Proc. NIPS
, pp. 963-971
-
-
Soudry, D.1
Hubara, I.2
Meir, R.3
-
73
-
-
0242611592
-
Analog implementation of ANN with inherent quadratic nonlinearity of the synapses
-
Sep.
-
M. Milev and M. Hristov, "Analog implementation of ANN with inherent quadratic nonlinearity of the synapses," IEEE Trans. Neural Netw., vol. 14, no. 5, pp. 1187-1200, Sep. 2003.
-
(2003)
IEEE Trans. Neural Netw.
, vol.14
, Issue.5
, pp. 1187-1200
-
-
Milev, M.1
Hristov, M.2
-
74
-
-
80855156709
-
Sub-nanosecond switching of a tantalum oxide memristor
-
Dec.
-
A. C. Torrezan, J. P. Strachan, G. Medeiros-Ribeiro, and R. S. Williams, "Sub-nanosecond switching of a tantalum oxide memristor," Nanotechnology, vol. 22, no. 48, p. 485203, Dec. 2011.
-
(2011)
Nanotechnology
, vol.22
, Issue.48
, pp. 485203
-
-
Torrezan, A.C.1
Strachan, J.P.2
Medeiros-Ribeiro, G.3
Williams, R.S.4
|